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| december 2001 1/111 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. rev. 2.0 st7flite0 8-bit mcu with single voltage flash memory, data eeprom, adc, timers, spi preliminary data n memories 1.5k bytes single voltage extended flash (xflash) program memory with read-out pro- tection, in-circuit programming and in-appli- cation programming (icp and iap) 128 bytes ram 128 bytes data eeprom with read-out pro- tection n clock, reset and supply management enhanced reset system enhanced low voltage supervisor (lvd) for main supply with 3 programmable reset thresholds and auxiliary voltage detector (avd) with interrupt capability for implement- ing safe power-down procedures clock sources: internal 1mhz rc 1% oscilla- tor or external clock optional pll x4 or x8 for 4 or 8 mhz internal clock four power saving modes: halt, active-halt, wait and slow n interrupt management 10 interrupt vectors plus trap and reset 4 external interrupt lines (on 4 vectors) n i/o ports 13 multifunctional bidirectional i/o lines 9 alternate function lines 6 high sink outputs n 2 timers one 8-bit lite timer with prescaler including: watchdog, 1 realtime base and 1 input cap- ture. one 12-bit auto-reload timer with output compare function and pwm n 1 communication interface spi synchronous serial interface n a/d converter 5 input channels fixed gain op-amp for 11-bit precision in 0 to 250 mv range (@ 5v v dd ) 8-bit precision for 0 to 5v (@ 5v v dd ) n instruction set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction true bit manipulation n development tools full hardware/software development package device summary dip16 so16 150o features st7flite09 st7flite05 program memory - bytes 1.5k flash 1.5k flash ram (stack) - bytes 128 (64) 128 (64) data eeprom - bytes 128 - peripherals lite timer w/ watchdog, autoreload timer w/ 1 pwm, spi, 8-bit adc w/ op-amp operating supply 2.4v to 5.5v cpu frequency 1mhz rc 1% pllx4/8mhz operating temperature -0 c to +70 c / -40 c to +85 c/ -40 cto+125 c packages so16 150o, dip16 so16 150o, dip16 1
table of contents 111 2/111 1 introduction . . . . . . . . . . . . . . . . . . . . . ......................................... 4 2 pin description . . . . . . . . . . . . ........................................... ..... 5 3 register & memory map . . . ............................. .................... 7 4 flash program memory . . . . . . . . . . . . . . . . . ................................. 10 4.1 introduction . ...................................................... 10 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 10 4.3 programming modes . ............................................... 10 4.4 program memory read-out protection . . . . . . . . . . . . . . . . . . . . . ........ 10 4.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 11 5 data eeprom . . . . . . . . . .................................................... 12 5.1 introduction . ...................................................... 12 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 12 5.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 13 5.4 power saving modes . . . . . . ......................................... 15 5.5 access error handling . . . . . . . . . . . ................................. 15 5.6 data eeprom read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . ........ 15 5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 16 6 central processing unit . . ............................................... 17 6.1 introduction . ...................................................... 17 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 17 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . ................................. 17 7 supply, reset and clock management . . . . ................................ 20 7.1 internal rc oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . ........ 20 7.2 phase locked loop . . . . . . . . . . . . . . . . ................................. 20 7.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 21 7.4 reset sequence manager (rsm) . . . . . ................................ 23 7.5 system integrity management (si) .................................. 25 8 interrupts . . ......................... .................................... 30 8.1 non maskable software interrupt . . . . . . ........................... 30 8.2 external interrupts . . . . . . . . . . . . . .................................. 30 8.3 peripheral interrupts . . ........................................... 30 9 power saving modes . . . . . . . . . . ........................................... 33 9.1 introduction . ...................................................... 33 9.2 slow mode . . . . . . . . . . . . . . ........................................... 33 9.3 wait mode . . . . . . . . . . . ............................................... 34 9.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 i/o ports . . . .............................................................. 37 10.1 introduction . ...................................................... 37 10.2 functional description . . . . ........................................ 37 10.3 i/o port implementation . . . . ........................................ 40 10.4 unused i/o pins . . . . . . . . . . . . . . . . . . . . ................................. 40 10.5 low power modes . . . . . . . . . . . . . . . . . ................................. 40 2 table of contents 3/111 10.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 40 11 on-chip peripherals . . . . . . ............................................... 42 11.1 lite timer (lt) . .................. .................................... 42 11.2 12-bit autoreload timer (at) . . . . ................................ .... 46 11.3 serial peripheral interface (spi) . .................................. 52 11.4 8-bit a/d converter (adc) ........................................... 64 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . ............................. .... 68 12.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.2 instruction groups . . . . . . . . . . . . . . . . . . .............................. 71 13 electrical characteristics . . . . ......................................... 74 13.1 parameter conditions . . . . . . . . . . . . . . . . .............................. 74 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.3 operating conditions . . . . . . . . . . .................................... 76 13.4 supply current characteristics . . . ................................ 81 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . ........... 83 13.6 memory characteristics . . . ........................................ 84 13.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.8 i/o port pin characteristics ........................................ 90 13.9 control pin characteristics . . . . . .................................. 95 13.10 communication interface characteristics . . . . . .................... 97 13.11 8-bit adc characteristics . . . . . . . . .................................. 99 14 package characteristics . . . . . . ........................................ 102 14.1 package mechanical data . . . . . . . . . . . . ............................. 102 14.2 thermal characteristics . . . . . . . . . . . ............................... 103 14.3 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . ....... 104 15 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 105 15.1 option bytes . . . ................................. .................. 105 15.2 device ordering information . . . . . . . . . ............................. 106 15.3 development tools . . . . . . . . . . . . . . . . . . . . . .......................... 107 15.4 st7 application notes . . . . . . . . . . . . ................................. 108 15.5 to get more information . . . ....................................... 109 16 summary of changes . . . . . . . . .......................................... 110 3 st7flite0 4/111 1 introduction the st7flite0 is a member of the st7 microcon- troller family. all st7 devices are based on a com- mon industry-standard 8-bit core, featuring an en- hanced instruction set. the st7flite0 features flash memory with byte-by-byte in-circuit programming (icp) and in- application programming (iap) capability. under software control, the st7flite0 device can be placed in wait, slow, or halt mode, re- ducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. for easy reference, all parametric data are located in section 13 on page 74. figure 1. general block diagram 8-bit core alu address and data bus reset port b port a spi 8-bit adc w/ wat chdog pb4:0 (5 bits) 1 mhz. rc osc internal clock control ram (128 bytes) pa7:0 (8 bits) v ss v dd power supply flash (1.5k bytes) lvd/avd + pll x 4 or x 8 lite timer memory data eeprom (128 bytes) 12-bit auto- reload timer 1 st7flite0 5/111 2 pin description figure 2. 16-pin package pinout (150mil) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v ss v dd ss/ain0/pb0 clkin/ain4/pb4 mosi/ain3/pb3 miso/ain2/pb2 sck/ain1/pb1 reset pa0 (hs)/ltic pa1 (hs) pa7 pa6/mco/iccclk pa5 (hs)/iccdata pa4 (hs) pa3 (hs) pa2 (hs)/atpwm0 ei1 ei0 (hs) 20ma high sink capability ei x associated external interrupt vector ei2 ei3 1 st7flite0 6/111 pin description (cont'd) legend / abbreviations for table 1 : type: i = input, o = output, s = supply in/output level: c= cmos 0.15v dd /0.85v dd with input trigger c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: input: float = floating, wpu = weak pull-up, int = interrupt 1) , ana = analog output: od = open drain 2) , pp = push-pull refer to see ai/o portso on page 37. for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold which is valid as long as the device is in reset state. table 1. device pin description note: in the interrupt input column, aei x o defines the associated external interrupt vector. if the weak pull-up col- umn (wpu) is merged with the interrupt column (int), then the i/o configuration is pull-up interrupt input, else the configuration is floating interrupt input. pin n pin name type level port / control main function (after reset) alternate functio n input output input output float wpu int ana od pp 1v ss s ground 2v dd s main power supply 3 reset i/o c t x x top priority non maskable interrupt (active low) 4 pb0/ain0/ss i/o c t x ei3 x x port b0 adc analog input 0 or spi slave select (active low) 5 pb1/ain1/sck i/o c t x xxx port b1 adc analog input 1 or spi serial clock 6 pb2/ain2/miso i/o c t x xxx port b2 adc analog input 2 or spi master in/ slave out data 7 pb3/ain3/mosi i/o c t x ei2 x x port b3 adc analog input 3 or spi master out / slave in data 8 pb4/ain4/clkin i/o c t x xxx port b4 adc analog input 4 or external clock input 9 pa7 i/o c t x ei1 x x port a7 10 pa6 /mco/iccclk i/o c t x xxx port a6 main clock output/in circuit com- munication clock 11 pa5/ iccdata i/o c t hs x xxx port a5 in circuit communication data 12 pa4 i/o c t hs x xxx port a4 13 pa3 i/o c t hs x xxx port a3 14 pa2/atpwm0 i/o c t hs x xxx port a2 auto-reload timer pwm0 15 pa1 i/o c t hs x xxx port a1 16 pa0/ltic i/o c t hs x ei0 x x port a0 lite timer input capture 1 st7flite0 7/111 3 register & memory map as shown in figure 3, the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, 128 bytes of ram, 128 bytes of data eeprom and 1.5 kbytes of user program memory. the ram space includes up to 64 bytes for the stack from 0c0h to 0ffh. the highest address bytes contain the user reset and interrupt vectors. the size of flash sector 0 is configurable by op- tion byte. figure 3. memory map 0000h ram flash memory (1.5k) interrupt & reset vectors hw registers 0080h 007fh 0fffh (see table 2) 1000h 107fh ffe0h ffffh (see table 4) 0100h reserved 00ffh short addressing ram (zero page) 64 bytes stack 00c0h 00ffh 0080h 00bfh (128 bytes) data eeprom (128 bytes) fa00h 1080h f9ffh reserved ffdfh 1 kbytes 0.5 kbytes sector 1 sector 0 1.5k flash ffff h fc00h fbffh fa00h program memory 1 st7flite0 8/111 register and memory map (cont'd) legend : x=undefined, r/w=read/write table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register 00h 1) 00h 40h r/w r/w r/w 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 1) 00h 00h r/w r/w r/w 2) 0006h to 000ah reserved area (5 bytes) 000bh 000ch lite timer ltcsr lticr lite timer control/status register lite timer input capture register xxh xxh r/w read only 000dh 000eh 000fh 0010h 0011h 0012h 0013h auto-reload timer atcsr cntrh cntrl atrh atrl pwmcr pwm0csr timer control/status register counter register high counter register low auto-reload register high auto-reload register low pwm output control register pwm 0 control/status register 00h 00h 00h 00h 00h 00h 00h r/w read only read only r/w r/w r/w r/w 0014h to 0016h reserved area (3 bytes) 0017h 0018h auto-reload timer dcr0h dcr0l pwm 0 duty cycle register high pwm 0 duty cycle register low 00h 00h r/w r/w 0019h to 002eh reserved area (22 bytes) 0002fh flash fcsr flash control/status register 00h r/w 00030h eeprom eecsr data eeprom control/status register 00h r/w 0031h 0032h 0033h spi spidr spicr spicsr spi data i/o register spi control register spi control/status register xxh 0xh 00h r/w r/w r/w 0034h 0035h 0036h adc adccsr adcdat adcamp a/d control status register a/d data register a/d amplifier control register 00h xxh 00h r/w read only r/w 0037h itc eicr external interrupt control register 00h r/w 0038h mcc mccsr main clock control/status register 00h r/w 1 st7flite0 9/111 notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 0039h 003ah clock and reset rccr sicsr rc oscillator control register system integrity control/status register 00h 0xh r/w r/w 003bh to 007fh reserved area (45 bytes) address block register label register name reset status remarks 1 st7flite0 10/111 4 flash program memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on-board using in-circuit programming or in-application program- ming. the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features n icp (in-circuit programming) n iap (in-application programming) n ict (in-circuit testing) for downloading and executing user application test patterns in ram n sector 0 size configurable by option byte n read-out and write protection against piracy 4.3 programming modes the st7 can be programmed in three different ways: insertion in a programming tool. in this mode, flash sectors 0 and 1, option byte row and data eeprom can be programmed or erased. in-circuit programming. in this mode, flash sectors 0 and 1, option byte row and data eeprom can be programmed or erased with- out removing the device from the application board. in-application programming. in this mode, sector 1 and data eeprom can be pro- grammed or erased without removing the de- vice from the application board and while the application is running. 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit commu- nication) which allows an st7 plugged on a print- ed circuit board (pcb) to communicate with an ex- ternal programming device connected via cable. this cable connected the icc interface on the ap- plication board to the programming tool see figure 4. icp is performed in three steps: switch the st7 to icc mode (in-circuit communi- cations). this is done by driving a specific signal sequence on the iccclk/data pins while the reset pin is pulled low. when the st7 enters icc mode, it fetches a specific reset vector which points to the st7 system memory contain- ing the icc protocol routine. this routine enables the st7 to receive bytes from the icc interface in order to: download icp_driver code in ram from the ic- cdata pin execute icp_driver code in ram to program the flash memory depending on the icp_driver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in application programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). this mode is fully controlled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) iap mode can be used to program any memory ar- eas except sector 0, which is write/erase protect- ed to allow recovery in case errors occur during the programming operation. 4.3.3 related documentation for more information, refer to the st7 flash pro- gramming reference manual and the st7 icc reference manual. 4.4 program memory read-out protection the read-out protection is enabled through an op- tion bit (see section 15.1 on page 105). when this option is selected, the programs and data stored in the program memory (flash or rom) are protected against read-out piracy (in- cluding a re-write protection). in flash devices, when this protection is removed by reprogram- ming the option byte, the entire program memory and data eeprom is first automatically erased. note: both program memory and data eeprom are protected using the same option bit. 1 st7flite0 11/111 flash program memory (cont'd) figure 4. typical icc interface icp needs a minimum of 4 and up to 6 pins to be connected to the programming tool. these pins are: reset: device reset v ss : device power supply ground iccclk: icc output serial clock pin iccdata: icc input serial data pin clkin: main clock input for external source v dd : application board power supply cautions: 1. if reset, iccclk or iccdata pins are used for other purposes in the application, a serial resis- tor has to be implemented to avoid a conflict in case one of the other devices forces the signal lev- el. if these pins are used as outputs in the applica- tion, the serial resistors are not necessary. as soon as the external controller is plugged to the board, the iccclk and iccdata pins cannot be used for other purposes. 2. if the osc option bit (rc oscillator selection) is set unintentionally, an external clock must be pro- vided via clkin to reprogram the device via icp (the st7 clock has to be running). 3. the use of pin 7 of the icc connector depends on the programming tool architecture. please re- fer to the documentation of the tool. this pin must be connected when using st programming tools (it is used to monitor the application power supply). 4.5 register description flash control/status register (fcsr) read/write reset value: 000 0000 (00h) 1st rass key: 0101 0110 (56h) 2nd rass key: 1010 1110 (aeh) note: this register is reserved for programming using icp, iap or other programming methods. for details on xflash programming, refer to the st7 flash programming reference manual. when an epb or another programming tool is used (in socket or icp mode), the rass keys are sent automatically. icc connector iccdata iccclk reset clkin vdd st7 mcu he10 connector type >2.7k w applicati on power supply optional (see caution 1) 1 2 4 6 8 10 975 3 optional (see caution 2) programming tool icc connector applicatio n board icc cable optional (see caution 3) 70 0 0 0 0 0 opt lat pgm 1 st7flite0 12/111 5 data eeprom 5.1 introduction the electrically erasable programmable read only memory can be used as a non volatile back- up for storing data. using the eeprom requires a basic access protocol described in this chapter. 5.2 main features n up to 32 bytes programmed in the same cycle n eeprom mono-voltage (charge pump) n chained erase and programming cycles n internal control of the global programming cycle duration n wait mode management n readout protection against piracy figure 5. eeprom block diagram eecsr high voltage pump 0 e2lat 0 0000 e2pgm eeprom memory matrix (1 row = 32 x 8 bits) address decoder data multiplexer 32 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus 1 st7flite0 13/111 data eeprom (cont'd) 5.3 memory access the data eeprom memory read/write access modes are controlled by the e2lat bit of the eep- rom control/status register (eecsr). the flow- chart in figure 6 describes these different memory access modes. read operation (e2lat=0) the eeprom can be read as a normal rom loca- tion when the e2lat bit of the eecsr register is cleared. in a read cycle, the byte to be accessed is put on the data bus in less than 1 cpu clock cycle. this means that reading data from eeprom takes the same time as reading data from eprom, but this memory cannot be used to exe- cute machine code. write operation (e2lat=1) to access the write mode, the e2lat bit has to be set by software (the e2pgm bit remains cleared). when a write access to the eeprom area occurs, the value is latched inside the 32 data latches ac- cording to its address. when pgm bit is set by the software, all the previ- ous bytes written in the data latches (up to 32) are programmed in the eeprom cells. the effective high address (row) is determined by the last eep- rom write sequence. to avoid wrong program- ming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four least significant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously. note : care should be taken during the program- ming cycle. writing to the same memory location will over-program the memory (logical and be- tween the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the e2lat bit. it is not possible to read the latched data. this note is ilustrated by the figure 8. figure 6. data eeprom programming flowchart read mode e2lat=0 e2pgm=0 write mode e2lat=1 e2pgm=0 read bytes in eeprom area write up to 32 bytes in eeprom area (with the same 11 msb of the address) start programming cycle e2lat=1 e2pgm=1 (set by software) e2lat 01 cleared by hardware 1 st7flite0 14/111 data eeprom (cont'd) figure 7. data e 2 prom write operation note: if a programming cycle is interrupted (by software or a reset action), the integrity of the data in mem- ory is not guaranteed. byte 1 byte 2 byte 32 phase 1 programming cycle read operation impossible phase 2 read operation possible e2lat bit e2pgm bit writing data latches waiting e2pgm and e2lat to fall set by user application cleared by hardware ? row / byte ? 0 1 2 3 ... 30 31 physical address 0 00h...1fh 1 20h...3fh ... n nx20h...nx20h+1fh row definition 1 st7flite0 15/111 data eeprom (cont'd) 5.4 power saving modes wait mode the data eeprom can enter wait mode on ex- ecution of the wfi instruction of the microcontrol- ler. the data eeprom will immediately enter this mode if there is no programming in progress, otherwise the data eeprom will finish the cycle and then enter wait mode. halt mode the data eeprom immediately enters halt mode if the microcontroller executes the halt in- struction. therefore the eeprom will stop the function in progress, and data may be corrupted. 5.5 access error handling if a read access occurs while e2lat=1, then the data bus will not be driven. if a write access occurs while e2lat=0, then the data on the bus will not be latched. if a programming cycle is interrupted (by software/ reset action), the memory data will not be guar- anteed. 5.6 data eeprom read-out protection the read-out protection is enabled through an op- tion bit (see section 15.1 on page 105). when this option is selected, the programs and data stored in the eeprom memory are protected against read-out piracy (including a re-write pro- tection). in flash devices, when this protection is removed by reprogramming the option byte, the entire program memeory and eeprom is first au- tomatically erased. note: both program memory and data eeprom are protected using the same option bit. figure 8. data eeprom programming cycle lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage 1 st7flite0 16/111 data eeprom (cont'd) 5.7 register description eeprom control/status register (eec- sr) read/write reset value: 0000 0000 (00h) bits 7:2 = reserved, forced by hardware to 0. bit 1 = e2lat latch access transfer this bit is set by software. it is cleared by hard- ware at the end of the programming cycle. it can only be cleared by software if the e2pgm bit is cleared. 0: read mode 1: write mode bit 0 = e2pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware. 0: programming finished or not yet started 1: programming cycle is in progress note : if the e2pgm bit is cleared during the pro- gramming cycle, the memory data is not guaran- teed table 3. data eeprom register map and reset values 70 000000 e2lat e2pgm address (hex.) register label 76543210 000ah eecsr reset value 000000 e2lat 0 e2pgm 0 1 st7flite0 17/111 6 central processing unit 6.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 main features n 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes n two 8-bit index registers n 16-bit stack pointer n low power modes n maskable hardware interrupts n non-maskable software interrupt 6.3 cpu registers the 6 cpu registers shown in figure 9 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 9. cpu registers accumulator x index register y index register stack pointer conditio n code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 87 0 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value 1 st7flite0 18/111 cpu registers (cont'd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the abit test and brancho, shift and rotate instructions. 70 111hinzc 1 st7flite0 19/111 cpu registers (cont'd) stack pointer (sp) read/write reset value: 00 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 10). since the stack is 64 bytes deep, the 10 most sig- nificant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp5 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 10. when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 10. stack manipulation example 15 8 00000000 70 1 1 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 00ffh @ 00c0h stack higher address = 00ffh stack lower address = 00c0h 1 st7flite0 20/111 7 supply, reset and clock management the device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. main features n clock management 1 mhz internal rc oscillator (enabled by op- tion byte) external clock input (enabled by option byte) pll for multiplying the frequency by 4 or 8 (enabled by option byte) n reset sequence manager (rsm) n system integrity management (si) main supply low voltage detection (lvd) with reset generation (enabled by option byte) auxiliary voltage detector (avd) with interrupt capability for monitoring the main supply (en- abled by option byte) 7.1 internal rc oscillator adjustment the st7flite0 contains an internal rc oscillator with an accuracy of 1% for a given device, temper- ature and voltage. it must be calibrated to obtain the frequency required in the application. this is done by software writing a calibration value in the rccr (rc control register). whenever the st7flite0 microcontroller is reset, the rccr returns to its default value (ffh), i.e. each time the device is reset, the calibration value must be loaded in the rccr. predefined calibra- tion values are stored in eeprom for 3.0 and 5v v dd supply voltages at 25 c, as shown in the fol- lowing table. notes: see aelectrical characteristicso on page 74. for more information on the frequency and accuracy of the rc oscillator. to improve clock stability, it is recommended to place a decoupling capacitor between the v dd and v ss pins as close as possible to the st7 de- vice. caution: if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. refer to application note an1324 for information on how to calibrate the rc frequency using an ex- ternal reference signal. 7.2 phase locked loop the pll can be used to multiply a 1mhz frequen- cy from the rc oscillator or the external clock by 4 or 8 to obtain f osc of 4 or 8 mhz. the pll is ena- bled and the multiplication factor of 4 or 8 is select- ed by 2 option bits. the x4 pll is intended for operation with v dd in the 2.4v to 3.3v range the x8 pll is intended for operation with v dd in the 3.3v to 5.5v range refer to section 15.1 for the option byte descrip- tion. if the pll is disabled and the rc oscillator is ena- bled, then f osc = 1mhz. if both the rc oscillator and the pll are disabled, f osc is driven by the external clock. figure 11. pll output frequency timing diagram when the pll output signal reaches the operating frequency, the locked bit in the sicscr register is set. full pll accuracy (acc pll ) is reached after a stabilisation time of t stab (see figure 11 and 13.3.4 internal rc oscillator and pll) refer to section 7.5.4 on page 29 for a description of the locked bit in the sicsr register. rccr condition s st7flite09 address st7flit e05 address rccr0 v dd =5v t a =25 c f rc =1mhz 1000h and ffddh ffddh rccr1 v dd =3.0v t a =25 c f rc =700khz 1001h and- ffdeh ffdeh 4/8 x freq. locked bit set t stab t lock input t output freq. 1 st7flite0 21/111 7.3 register description main clock control/status register (mccsr) read / write reset value: 0000 0000 (00h) bits 7:2 = reserved, must be kept cleared. bit 1 = mco main clock out enable this bit is read/write by software and cleared by hardware after a reset. this bit allows to enable the mco output clock. 0: mco clock disabled, i/o port free for general purpose i/o. 1: mco clock enabled. bit 0 = sms slow mode select this bit is read/write by software and cleared by hardware after a reset. this bit selects the input clock f osc or f osc /32. 0: normal mode (f cpu = f osc 1: slow mode (f cpu = f osc /32) rc control register (rccr) read / write reset value: 1111 1111 (ffh) bits 7:0 = cr[7:0] rc oscillator frequency ad- justment bits these bits must be written immediately after reset to adjust the rc oscillator frequency and to obtain an accuracy of 1%. the application can store the correct value for each voltage range in eeprom and write it to this register at start-up. 00h = maximum available frequency ffh = lowest available frequency note: to tune the oscillator, write a series of differ- ent values in the register until the correct frequen- cy is reached. the fastest method is to use a di- chotomy starting with 80h. 70 000000 mco sms 70 0000000 0 1 st7flite0 22/111 figure 12. clock management block diagram cr4 cr7 cr0 cr1 cr2 cr3 cr6 cr5 rccr tunable pll 1mhz -> 8mhz clkin option byte pll 1mhz -> 4mhz f osc 8mhz 4mhz 1mhz 0 to 8 mhz mccsr sms mco mco f cpu f cpu to cpu and peripherals (1ms timebase @ 8 mhz f osc ) /32 divider f osc f osc /32 f osc oscillator 1% rc f ltimer 1 0 option byte lite timer counter 8-bit /2 divider 7 0 (except lite timer) 1 st7flite0 23/111 7.4 reset sequence manager (rsm) 7.4.1 introduction the reset sequence manager includes three re- set sources as shown in figure 14: n external reset source pulse n illegal opcode reset n internal lvd reset (low voltage detection) n internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the active phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 13: n active phase depending on the reset source n 256 cpu clock cycle delay n reset vector fetch the 256 cpu clock cycle delay allows the oscilla- tor to stabilise and ensures that recovery has tak- en place from the reset state. the reset vector fetch phase duration is 2 clock cycles. figure 13. reset sequence phases note: whatever the reset source is (internal or ex- ternal), the user must ensure that the level on the reset pin can go below the v il max. level speci- fied in section 13.9.1 on page 95 . otherwise the reset will not be taken into account internally. caution: because the reset circuit is designed to allow an internal reset to act on the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-up for example) is less than the absolute maximum value specified for i inj(reset) in section 13.2.2 on page 75 . figure 14. reset block diagram reset active phase internal reset 256 clock cycles fetch vector reset r on v dd watchdog reset lvd reset internal reset pulse generator filter illegal opcode 1 st7flite0 24/111 reset sequence manager (cont'd) 7.4.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristics section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized. this detection is asynchro- nous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. if the external reset pulse is shorter than t w(rstl)out (see short ext. reset in figure 15), the signal on the reset pin will be stretched by a de- lay generated by the pulse generator. otherwise the delay will not be applied (see long ext. reset in figure 15). starting from the external reset pulse recogni- tion, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . 7.4.3 internal low voltage detection reset two different reset sequences caused by the in- ternal lvd circuitry can be distinguished: n power-on reset n voltage drop reset the device reset pin acts as an output that is pulled low when v dd st7flite0 26/111 figure 17. reset and supply management block diagram low voltage dete ctor (lvd) auxilia ry voltage dete ctor (avd) reset v ss v dd reset sequenc e manager (rsm) avd interrupt request system inte grity management watc hdog sicsr timer (wdg) avd avd lvd rf ie 0 f 0 status flag 0 0 loc ked 7 0 1 st7flite0 27/111 system integrity management (cont'd) 7.5.2 auxiliary voltage detector (avd) the voltage detector function (avd) is based on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main sup- ply. the v it-(avd) reference value for falling volt- age is lower than the v it+(avd) reference value for rising voltage in order to avoid parasitic detection (hysteresis). the output of the avd comparator is directly read- able by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. caution : the avd functions only if the lvd is en- abled through the option byte. 7.5.2.1 monitoring the v dd main supply the avd voltage threshold value is relative to the selected lvd threshold configured by option byte (see section 15.1 on page 105). if the avd interrupt is enabled, an interrupt is gen- erated when the voltage crosses the v it+(lvd) or v it-(avd) threshold (avdf bit is set). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcon- troller. see figure 18. the interrupt on the rising edge is used to inform the application that the v dd warning state is over figure 18. using the avd to monitor v dd v dd v it+(avd) v it-(avd) avdf bit 01 reset if avdie bit = 1 v hyst avd interrupt request interrupt cleared by v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 0 1 hardware interru pt cleared by reset 1 st7flite0 28/111 system integrity management (cont'd) 7.5.3 low power modes 7.5.3.1 interrupts the avd interrupt event generates an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is re- set (rim instruction). mode description wait no effect on si. avd interrupts cause the device to exit from wait mode. halt the crsr register is frozen. the avd remains active, and an avd inter- rupt can be used to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes yes 1 st7flite0 29/111 system integrity management (cont'd) 7.5.4 register description system integrity (si) control/status register (sicsr) read/write reset value: 0000 0x00 (0xh) bit 7:4 = reserved, must be kept cleared. bit 2 = lvdrf lvd reset flag this bit indicates that the last reset was generat- ed by the lvd block. it is set by hardware (lvd re- set) and cleared by software (writing zero). see wdgrf flag description in section 11.1 for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 1 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is gen- erated when the avdf bit changes value. refer to figure 18 for additional details 0: v dd over avd threshold 1: v dd under avd threshold bit 0 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag changes (toggles). the pending interrupt informa- tion is automatically cleared when software enters the avd interrupt routine. 0: avd interrupt disabled 1: avd interrupt enabled application notes the lvdrf flag is not cleared when another re- set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. 70 000 loc ked lvd rf avd f avd ie 1 st7flite0 30/111 8 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the interrupt mapping table and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 19. the maskable interrupts must be enabled by clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). note: after reset, all interrupts are disabled. when an interrupt has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. the i bit of the cc register is set to prevent addi- tional interrupts. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address- es). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt cannot be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the interrupt map- ping table). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifi- cally mentioned interrupts allow the processor to leave the halt low power mode (refer to the aexit from halta column in the interrupt mapping ta- ble). 8.1 non maskable software interrupt this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced according to the flowchart on figure 19. 8.2 external interrupts external interrupt vectors can be loaded into the pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins, connected to the same inter- rupt vector, are configured as interrupts, their sig- nals are logically nanded before entering the edge/level detection block. caution: the type of sensitivity defined in the mis- cellaneous or interrupt register (if available) ap- plies to the ei source. in case of a nanded source (as described on the i/o ports section), a low level on an i/o pin configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity. 8.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: the i bit of the cc register is cleared. the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: writing a0o to the corresponding bit in the status register or access to the status register while the flag is set followed by a read or write of an associated reg- ister. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed. 1 st7flite0 31/111 interrupts (cont'd) figure 19. interrupt processing flowchart table 4. interrupt mapping i bit set? y n iret? y n from reset load pc from interrupt vecto r stack pc, x, a, cc set i bit fetch next instr uction execu te instruction this clears i bit by default restore pc, x, a, cc from stack inte rrupt y n pending ? n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 not used fffah-fffbh 1 ei0 external interrupt 0 yes fff8h-fff9h 2 ei1 external interrupt 1 fff6h-fff7h 3 ei2 external interrupt 2 fff4h-fff5h 4 ei3 external interrupt 3 fff2h-fff3h 5 not used fff0h-fff1h 6 not used ffeeh-ffe fh 7 si avd interrupt sicsr yes ffech-ffedh 8 at timer at timer output compare interrupt pwm0csr no ffeah-ffebh 9 at timer overflow interrupt atcsr yes ffe8h-ffe9h 10 lite timer lite timer input capture interrupt ltcsr no ffe6h-ffe7h 11 lite timer rtc interrupt ltcsr yes ffe4h-ffe5h 12 spi spi peripheral interrupts spicsr yes ffe2h-ffe3h 13 not used ffe0h-ffe1h 1 st7flite0 32/111 interrupts (cont'd) external interrupt control register (eicr) read/write reset value: 0000 0000 (00h) bit 7:6 = is3[1:0] ei3 sensitivity these bits define the interrupt sensitivity for ei3 (port b0) according to table 5. bit 5:4 = is2[1:0] ei2 sensitivity these bits define the interrupt sensitivity for ei2 (port b3) according to table 5. bit 3:2 = is1[1:0] ei1 sensitivity these bits define the interrupt sensitivity for ei1 (port a7) according to table 5. bit 1:0 = is0[1:0] ei0 sensitivity these bits define the interrupt sensitivity for ei0 (port a0) according to table 5. note: these 8 bits can be written only when the i bit in the cc register is set. table 5. interrupt sensitivity bits . 70 is31 is30 is21 is20 is11 is10 is01 is00 isx1 isx0 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge 1 st7flite0 33/111 9 power saving modes 9.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 20): slow, wait (slow wait), ac- tive halt and halt. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (f osc ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the oscillator status. figure 20. power saving mode transitions 9.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu )to the available supply voltage. slow mode is controlled by the sms bit in the mccsr register which enables or disables slow mode. in this mode, the oscillator frequency is divided by 32. the cpu and peripherals are clocked at this- lower frequency. notes : slow-wait mode is activated when entering wait mode while the device is already in slow mode. slow mode has no effect on the lite timer which is already clocked at f osc/32 . figure 21. slow mode clock transition power consumption wait slow run active halt high low slow wait halt sms f cpu normal run mode request f osc f osc /32 f osc 1 st7flite0 34/111 power saving modes (cont'd) 9.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the `wfi' instruction. all peripherals remain active. during wait mode, the i bit of the cc register is cleared, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the pro- gram counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 22. figure 22. wait mode flow-chart note: 1. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals i bit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals i bit on off 0 on cpu oscillator peripherals i bit on on x 1) on 256 cpu clock cycle delay 1 st7flite0 35/111 power saving modes (cont'd) 9.4 active-halt and halt modes active-halt and halt modes are the two low- est power consumption modes of the mcu. they are both entered by executing the `halt' instruc- tion. the decision to enter either in active-halt or halt mode is given by the ltcsr/atcsr reg- ister status as shown in the following table:. 9.4.1 active-halt mode active-halt mode is the lowest power con- sumption mode of the mcu with a real time clock available. it is entered by executing the `halt' in- struction when active halt mode is enabled. the mcu can exit active-halt mode on recep- tion of a specific interrupt (see table 4, ainterrupt mapping,o on page 31) or a reset. when exiting active-halt mode by means of a reset, a 256 cpu cycle delay occurs. after the start up delay, the cpu resumes operation by fetching the reset vector which woke it up (see figure 24). when exiting active-halt mode by means of an interrupt, the cpu immediately resumes oper- ation by servicing the interrupt vector which woke it up (see figure 24). when entering active-halt mode, the i bit in the cc register is cleared to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, only the main oscillator and the selected timer counter (lt/at) are running to keep a wake-up time base. all other peripherals are not clocked except those which get their clock supply from another clock generator (such as ex- ternal or auxiliary oscillator). caution: as soon as active-halt is enabled, executing a halt instruction while the watchdog is active does not generate a reset if the wdghalt bit is reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 23. active-halt timing overview figure 24. active-halt mode flow-chart notes: 1. this delay occurs only if the mcu exits active- halt mode by means of a reset. 2. peripherals clocked with an external clock source can still be active. 3. only the lite timer rtc interrupt and some specific interrupts can exit the mcu from active- halt mode (such as external interrupt). refer to table 4, ainterrupt mapping,o on page 31 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. ltcsr tbie bit atcsr ovfie bit atcsr ck1 bit atcsr ck0 bit meaning 0xx0 active-halt mode disabled 00xx 0111 1xxx active-halt mode enabled x101 halt run run 256 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [active halt enabled] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i bit on off 0 off fetch reset vector or service interrupt cpu oscillator peripherals 2) i bit on off x 4) on cpu oscillator peripherals i bits on on x 4) on 256 cpu clock cycle delay (active halt enabled) 1 st7flite0 36/111 power saving modes (cont'd) 9.4.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the `halt' instruction when active halt mode is disa- bled. the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 4, ainterrupt mapping,o on page 31) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 256 cpu cycle delay is used to stabilize the oscillator. after the start up delay, the cpu resumes opera- tion by servicing the interrupt or by fetching the re- set vector which woke it up (see figure 26). when entering halt mode, the i bit in the cc reg- ister is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes immedi- ately. in halt mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of watchdog operation with halt mode is configured by the awdghalto op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see sec- tion 15.1 on page 105 for more details). figure 25. halt timing overview figure 26. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 4, ainterrupt mapping,o on page 31 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. halt run run 256 cpu cycle delay reset or interrupt halt instruction fetch vector [active halt disabled] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i bit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals i bit on off x 4) on cpu oscillator peripherals i bits on on x 4) on 256 cpu clock cycle delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 (active halt disabled) 1 st7flite0 37/111 10 i/o ports 10.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 10.2 functional description each port has 2 main registers: data register (dr) data direction register (ddr) and one optional register: option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 27 10.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. note : writing the dr register modifies the latch value but does not affect the pin status. external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the mis- cellaneous register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several input pins are se- lected simultaneously as interrupt source, these are logically anded. for this reason if one of the interrupt pins is tied low, it masks the other ones. the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the miscellane- ous register must be modified. 10.2.2 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. then reading the dr reg- ister returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: note: when switching from input to output mode, the dr register has to be written first to drive the correct level on the pin as soon as the port is con- figured as an output. 10.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming under the following conditions: when the signal is coming from an on-chip pe- ripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripher- al, the i/o pin must be configured in floating input mode. in this case, the pin state is also digitally readable by addressing the dr register. notes : input pull-up configuration can cause unexpect- ed value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. dr push-pu ll open-drain 0v ss vss 1v dd floating 1 st7flite0 38/111 i/o ports (cont'd) figure 27. i/o port general block diagram table 6. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external source (ei x ) interrupt polarity selection cmos schmitt trigger register access 1 st7flite0 39/111 i/o ports (cont'd) table 7. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configu ration input 1) open-drain output 2) push-pull output 2) condition pad v dd r pu external interr upt polarity data bus pull-up interrupt dr register access w r from other pins source (ei x ) selection dr registe r conditio n alternate input analog input pad r pu data b us dr dr regist er access r/w v dd alternate alternate enable output regist er pad r pu data b us dr dr regist er access r/w v dd alternate alternate enable output regist er 1 st7flite0 40/111 i/o ports (cont'd) caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 10.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 28 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 28. interrupt i/o port state transitions 10.4 unused i/o pins unused i/o pins must be connected to fixed volt- age levels. refer to section 13.8. 10.5 low power modes 10.6 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes 1 st7flite0 41/111 i/o ports (cont'd) i/o port implementation the i/o port register configurations are summa- rised as follows. standard ports pa6:1, pb4, pb2:0 interrupt ports pa7, pa0, pb3, pb0 (with pull-up) mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 1 st7flite0 42/111 11 on-chip peripherals 11.1 lite timer (lt) 11.1.1 introduction the lite timer can be used for general-purpose timing functions. it is based on a free-running 13- bit upcounter with two software-selectable time- base periods, an 8-bit input capture register and watchdog function. 11.1.2 main features n realtime clock 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 mhz f osc ) maskable timebase interrupt n input capture 8-bit input capture register (lticr) maskable interrupt with wakeup from halt mode capability n watchdog enabled by hardware or software (configura- ble by option byte) optional reset on halt instruction (configura- ble by option byte) automatically resets the device unless disable bit is refreshed software reset (forced watchdog reset) watchdog reset status flag figure 29. lite timer block diagram ltcsr watchdog 8-bit upcounter /2 8-bit f ltimer f wdg 8 ltic f osc /32 wdgd wdge wdg tbf tbie tb icf icie watchdog reset lttb interrupt request ltic interrupt request lticr input capture register 1 0 1or2ms timebase (@ 8mhz f osc ) to 12-bit at timer f ltimer rf 0 7 1 st7flite0 43/111 lite timer (cont'd) 11.1.3 functional description the value of the 8-bit counter cannot be read or written by software. after an mcu reset, it starts incrementing from 0 at a frequency of f osc /32. a counter overflow event occurs when the counter rolls over from f9h to 00h. if f osc = 8 mhz, then the time period between two counter overflow events is 1 ms. this period can be doubled by set- ting the tb bit in the ltcsr register. when the timer overflows, the tbf bit is set by hardware and an interrupt request is generated if the tbie is set. the tbf bit is cleared by software reading the ltcsr register. 11.1.3.1 watchdog when enabled using the wdge bit, the watchdog generates a reset after 2 ms (@ = 8 mhz f osc ). to prevent this watchdog reset occuring, software must set the wdgd bit. the wdgd bit is cleared by hardware after t wdg . this means that software must write to the wdgd bit at regular intervals to prevent a watchdog reset occurring. refer to fig- ure 30. note: software can use the timebase feature to set the wdgd bit at 1 or 2 ms intervals. a watchdog reset can be forced at any time by setting the wdgrf bit. the wdgrf bit also acts as a flag, indicating that the watchdog was the source of the reset. it is au- tomatically cleared after it has been read. caution: when the wdgrf bit is set, software must clear it, otherwise the next time the watchdog is enabled (by hardware or software), the micro- controller will be immediately reset. hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdge bit in the ltcsr is not used. refer to the option byte description in the odevice configuration and ordering informationo section. using halt mode with the watchdog (option) if the watchdog reset on halt option is not se- lected by option byte, the halt mode can be used when the watchdog is enabled. in this case, the halt instruction stops the oscilla- tor. when the oscillator is stopped, the lite timer stops counting and is no longer able to generate a watchdog reset until the microcontroller receives an external interrupt or a reset. if an external interrupt is received, the wdg re- starts counting after 256 cpu clocks. if a reset is generated, the watchdog is disabled (reset state). recommendations make sure that an external event is available to wake up the microcontroller from halt mode. before executing the halt instruction, refresh the wdgd bit, to avoid an unexpected watch- dog reset immediately after waking up the micro- controller. figure 30. watchdog timing diagram t wdg f wdg internal watchdog reset wdgd bit software sets wdgd bit hardware clears wdgd bit watchdog reset (2ms @ 8mhz f osc ) 1 st7flite0 44/111 lite timer (cont'd) when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ainput pull-up with interrupto before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. for the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). input capture the 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the icap1 pin. when an input cap- ture occurs, the icf bit is set and the lticr regis- ter contains the msb of the free-running up- counter. an interrupt is generated if the icie bit is set. the icf bit is cleared by reading the lticr register. the lticr is a read only register and always con- tains the data from the last input capture. input capture is inhibited if the icf bit is set. 11.1.4 low power modes 11.1.5 interrupts note: the tbf and icf interrupt events are con- nected to separate interrupt vectors (see inter- rupts chapter). they generates an interrupt if the enable bit is set in the ltcsr register and the interrupt mask in the cc register is reset (rim instruction). figure 31. input capture timing diagram. mode description slow no effect on lite timer (this peripheral is driven directly by f osc /32) wait no effect on lite timer halt no effect on lite timer interrupt event event flag enable control bit exit from wait exit from halt timebase event tbf tbie yes yes ic event icf icie yes no 04h 8-bit counter t 01h f osc /32 xxh 02h 03h 05h 06h 07h 04h ltic pin icf flag lticr register cleared 4 m s (@ 8mhz f osc ) f cpu by s/w 07h reading ltic register 1 st7flite0 45/111 lite timer (cont'd) 11.1.6 register description lite timer control/status register (ltcsr) read / write reset value: 0x00 0000 (x0h) bit 7 = icie interrupt enable. this bit is set and cleared by software. 0: input capture (ic) interrupt disabled 1: input capture (ic) interrupt enabled bit 6 = icf input capture flag. this bit is set by hardware and cleared by software by reading the lticr register. writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred note: after an mcu reset, software must initialise the icf bit by reading the lticr register bit 5 = tb timebase period selection. this bit is set and cleared by software. 0: timebase period = t osc * 8000 (1ms @ 8 mhz) 1: timebase period = t osc * 16000 (2ms @ 8 mhz) bit 4 = tbie timebase interrupt enable . this bit is set and cleared by software. 0: timebase (tb) interrupt disabled 1: timebase (tb) interrupt enabled bit 3 = tbf timebase interrupt flag . this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter overflow 1: a counter overflow has occurred bit 2 = wdgrf force reset/ reset status flag this bit is used in two ways: it is set by software to force a watchdog reset. it is set by hardware when a watchdog reset occurs and cleared by hardware or by software. it is cleared by hardware only when an lvd reset occurs. it can be cleared by software after a read access to the ltcsr register. 0: no watchdog reset occurred. 1: force a watchdog reset (write), or, a watchdog reset occurred (read). bit 1 = wdge watchdog enable this bit is set and cleared by software. 0: watchdog disabled 1: watchdog enabled bit 0 = wdgd watchdog reset delay this bit is set by software. it is cleared by hard- ware at the end of each t wdg period. 0: watchdog reset not delayed 1: watchdog reset delayed lite timer input capture register (lticr) read only reset value: 0000 0000 (00h) bit 7:0 = icr[7:0] input capture value these bits are read by software and cleared by hardware after a reset. if the icf bit in the ltcsr is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the ltic pin. table 8. lite timer register map and reset values 70 icie icf tb tbie tbf wdgr wdge wdgd 70 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 address (hex.) register label 76543210 0b ltcsr reset value icie 0 icf x tb 0 tbie 0 tbf 0 wdgrf 0 wdge 0 wdgd 0 0c lticr reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 1 st7flite0 46/111 11.2 12-bit autoreload timer (at) 11.2.1 introduction the 12-bit autoreload timer can be used for gen- eral-purpose timing functions. it is based on a free- running 12-bit upcounter with a pwm output chan- nel. 11.2.2 main features n 12-bit upcounter with 12-bit autoreload register (atr) n maskable overflow interrupt n pwm signal generator n frequency range 2khz-4mhz (@ 8 mhz f cpu ) programmable duty-cycle polarity control maskable compare interrupt n output compare function figure 32. block diagram atcsr cmpie ovfie ovf ck0 ck1 0 0 0 12-bit autoreload value 12-bit upcounter cmpf0 bit cmpf0 cmp interrupt request ovf interrupt request f cpu atr pwm generation pol- arity op0 bit pwm0 comp- pare 12-bit duty cycle value f counter f pwm output control oe0 bit cntr (1 ms timebase f ltimer dcr0h dcr0l update on ovf event preload preload @ 8mhz) 70 on ovf event if oe0=1 1 st7flite0 47/111 12-bit autoreload timer (cont'd) 11.2.3 functional description pwm mode this mode allows a pulse width modulated sig- nals to be generated on the pwm0 output pin with minimum core processing overhead. the pwm0 output signal can be enabled or disabled using the oe0 bit in the pwmcr register. when this bit is set the pwm i/o pin is configured as output push- pull alternate function. note: cmpf0 is available in pwm mode (see pwm0csr description on page 50). pwm frequency and duty cycle the pwm signal frequency (f pwm ) is controlled by the counter period and the atr register value. f pwm =f counter / (4096 - atr) following the above formula, if f cpu is 8 mhz, the maximum value of f pwm is 4 mhz (atr register value = 4094), and the minimum value is 2 khz (atr register value = 0). note: the maximum value of atr is 4094 be- cause it must be lower than the dcr value which must be 4095 in this case. at reset, the counter starts counting from 0. software must write the duty cycle value in the dcr0h and dcr0l preload registers. the dcr0h register must be written first. when a upcounter overflow occurs (ovf event), the atr value is loaded in the upcounter, the preloaded duty cycle value is transferred to the duty cycle register and the pwm0 signal is set to a high level. when the upcounter matches the dcrx value the pwm0 signals is set to a low level. to obtain a signal on the pwm0 pin, the contents of the dcr0 register must be greater than the con- tents of the atr register. the polarity bit can be used to invert the output signal. the maximum available resolution for the pwm0 duty cycle is: resolution = 1 / (4096 - atr) note : to get the maximum resolution (1/4096), the atr register must be 0. with this maximum reso- lution and assuming that dcr=atr, a 0% or 100% duty cycle can be obtained by changing the polarity . figure 33. pwm function figure 34. pwm signal example duty cycle register auto-reload register pwm0 output t 4095 000 with oe0=1 and op0=0 (atr) (dcr0) with oe0=1 and op0=1 counter counter pwm0 output t with oe0=1 and op0=0 ffdh ffeh fffh ffdh ffeh fffh ffdh ffeh dcr0=ffeh atr= ffdh f counter 1 st7flite0 48/111 12-bit autoreload timer (cont'd) output compare mode to use this function, the oe bit must be 0. soft- ware must then write a 12-bit value in the dcr0h and dcr0l registers. this value will be loaded im- mediately (without waiting for an ovf event). the dcr0h must be written first, the output com- pare function starts only when the dcr0l value is written. when the 12-bit upcounter (cntr) reaches the value stored in the dcr0h and dcr0l registers, the cmpr0 bit in the pwm0csr register is set and an interrupt request is generated if the cmpie bit is set. note: the output compare function is only availa- ble for dcrx values other than 0 (reset value). 11.2.4 low power modes 11.2.5 interrupts note: the interrupt events are connected to sepa- rate interrupt vectors (see interrupts chapter). they generates an interrupt if the enable bit is set in the atcsr register and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on at timer halt at timer halted. interrupt event event flag enable control bit exit from wait exit from halt overflow event ovff tbie yes yes cmp event cmpfx cmpie yes no 1 st7flite0 49/111 12-bit autoreload timer (cont'd) 11.2.6 register description timer control status register (atc- sr) read / write reset value: 0000 0000 (00h) bit 7:5 = reserved, must be kept cleared. bit 3:4 = ck[1:0] counter clock selection. these bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. bit 2 = ovf overflow flag. this bit is set by hardware and cleared by software by reading the atcsr register. it indicates the transition of the counter from ffh to atr value. 0: no counter overflow occurred 1: counter overflow occurred caution: when set, the ovf bit stays high for 1 f counter cycle, (up to 1ms depending on the clock selec- tion). bit 1 = ovfie overflow interrupt enable. this bit is read/write by software and cleared by hardware after a reset. 0: ovf interrupt disabled 1: ovf interrupt enabled bit 0 = cmpie compare interrupt enable . this bit is read/write by software and clear by hardware after a reset. it allows to mask the inter- rupt generation when cmpf bit is set. 0: cmpf interrupt disabled 1: cmpf interrupt enabled counter register high (cntrh) read only reset value: 0000 0000 (00h) counter register low (cntrl) read only reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared. bits 11:0 = cntr[11:0] counter value . this 12-bit register is read by software and cleared by hardware after a reset. the counter is incre- mented continuously as soon as a counter clock is selected. to obtain the 11-bit value, software should read the counter value in two consecutive read operations, lsb first. when a counter over- flow occurs, the counter restarts from the value specified in the atr register. 70 0 0 0 ck1 ck0 ovf ovfie cmpie counter clock selection ck1 ck0 off 0 0 f ltimer (1 ms timebase @ 8 mhz) 0 1 f cpu 10 reserved 1 1 15 8 0 0 0 0 cn11 cn10 cn9 cn8 70 cn7 cn6 cn5 cn4 cn3 cn2 cn1 cn0 1 st7flite0 50/111 12-bit autoreload timer (cont'd) auto reload register (atrh) read / write reset value: 0000 0000 (00h) auto reload register (atrl) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared. bits 11:0 = atr[11:0] autoreload register. this is a 12-bit register which is written by soft- ware. the atr register value is automatically loaded into the upcounter when an overflow oc- curs. the register value is used to set the pwm frequency. pwm0 duty cycle register high (dcr0h) read / write reset value: 0000 0000 (00h) pwm0 duty cycle register low (dcr0l) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared. bits 11:0 = dcr[11:0] pwmx duty cycle value this 12-bit value is written by software. the high register must be written first. in pwm mode (oe0=1 in the pwmcr register) the dcr[11:0] bits define the duty cycle of the pwm0 output signal (see figure 33 ) . in output compare mode, (oe0=0 in the pwmcr register) they define the value to be compared with the 12- bit upcounter value. pwm0 control/status register (pwm0csr) read / write reset value: 0000 0000 (00h) bit 7:2= reserved, must be kept cleared. bit 1 = op0 pwm0 output polarity. this bit is read/write by software and cleared by hardware after a reset. this bit selects the polarity of the pwm0 signal. 0: the pwm0 signal is not inverted. 1: the pwm0 signal is inverted. bit 0 = cmpf0 pwm0 compare flag. this bit is set by hardware and cleared by software by reading the pwm0csr register. it indicates that the upcounter value matches the dcr0 regis- ter value. 0: upcounter value does not match dcr value. 1: upcounter value matches dcr value. 15 8 0000 atr11 atr10 atr9 atr8 70 atr7 atr6 atr5 atr4 atr3 atr2 atr1 atr0 15 8 0000 dcr11 dcr10 dcr9 dcr8 70 dcr7 dcr6 dcr5 dcr4 dcr3 dcr2 dcr1 dcr0 70 0 0 0 0 0 0 op0 cmpf0 1 st7flite0 51/111 12-bit autoreload timer (cont'd) pwm output control register (pwmcr) read/write reset value: 0000 0000 (00h) bits 7:1 = reserved, must be kept cleared. bit 0 = oe0 pwm0 output enable . this bit is set and cleared by software. 0: pwm0 output alternate function disabled (i/o pin free for general purpose i/o) 1: pwm0 output enabled table 9. register map and reset values 70 0000000oe0 address (hex.) register label 76543210 0d atcsr reset value 000 ck1 0 ck0 0 ovf 0 ovfie 0 cmpie 0 0e cntrh reset value 0000 cn11 0 cn10 0 cn9 0 cn8 0 0f cntrl reset value cn7 0 cn8 0 cn7 0 cn6 0 cn3 0 cn2 0 cn1 0 cn0 0 10 atrh reset value 0000 atr11 0 atr10 0 atr9 0 atr8 0 11 atrl reset value atr7 0 atr6 0 atr5 0 atr4 0 atr3 0 atr2 0 atr1 0 atr0 0 12 pwmcr reset value 0000000 oe0 0 13 pwm0csr reset value 000000 op 0 cmpf0 0 17 dcr0h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 18 dcr0l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1 st7flite0 52/111 11.3 serial peripheral interface (spi) 11.3.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.3.2 main features n full duplex synchronous transfers (on 3 lines) n simplex synchronous transfers (on 2 lines) n master or slave operation n six master mode frequencies (f cpu /4 max.) n f cpu /2 max. slave mode frequency n ss management by software or hardware n programmable clock polarity and phase n end of transfer interrupt flag n write collision, master mode fault and overrrun flags 11.3.3 general description figure 35 shows the serial peripheral interface (spi) block diagram. there are 3 registers: spi control register (spicr) spi control/status register (spicsr) spi data register (spidr) the spi is connected to external devices through 3 pins: miso: master in / slave out data mosi: master out / slave in data sck: serial clock out by spi masters and in- put by spi slaves ss: slave select: this input signal acts as a `chip select' to let the spi master communicate with slaves indi- vidually and to avoid contention on the data lines. slave ss inputs can be driven by stand- ard i/o ports on the master mcu. figure 35. serial peripheral interface block diagram spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0 1 st7flite0 53/111 serial peripheral interface (cont'd) 11.3.3.1 functional description a basic example of interconnections between a single master and a single slave is illustrated on figure 36. the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by the mas- ter. when the master device transmits data to a slave device via mosi pin, the slave device re- sponds by sending data to the master device via the miso pin. this implies full duplex communica- tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node ( in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 39) but master and slave must be programmed with the same timing mode. figure 36. single master/ single slave application 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software 1 st7flite0 54/111 serial peripheral interface (cont'd) 11.3.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr regis- ter (see figure 38) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 37): if cpha=1 (data latched on 2nd clock edge): ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by manag- ing the ss function by software (ssm= 1 and ssi=0 in the in the spicsr register) if cpha=0 (data latched on 1st clock edge): ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 11.3.5.3). figure 37. generic ss timing diagram figure 38. hardware/software slave select management mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin 1 st7flite0 55/111 serial peripheral interface (cont'd) 11.3.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). to operate the spi in master mode, perform the following two steps in order (if the spicsr register is not written first, the spicr register setting may be not taken into account): 1. write to the spicsr register: select the clock frequency by configuring the spr[2:0] bits. select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 39 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 2. write to the spicr register: set the mstr and spe bits note: mstr and spe bits remain set only if ss is high). the transmit sequence begins when software writes a byte in the spidr register. 11.3.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most sig- nificant bit first. when data transfer is complete: the spif bit is set by hardware an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. 11.3.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the fol- lowing actions: select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 39). note: the slave must have the same cpol and cpha settings as the master. manage the ss pin as described in section 11.3.3.2 and figure 37. if cpha=1 ss must be held low continuously. if cpha=0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and set the spe bit to enable the spi i/o functions. 11.3.3.6 slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most sig- nificant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: the spif bit is set by hardware an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set. 2. a write or a read to the spidr register. notes: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 11.3.5.2). 1 st7flite0 56/111 serial peripheral interface (cont'd) 11.3.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 39). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 39, shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. figure 39. data clock timing diagram sck msbi t bi t 6 bit 5 bi t 4 bit3 bit 2 bi t 1 lsbi t msbit bit 6 bit 5 bi t 4 bi t3 bit 2 bit 1 lsbit miso (frommaster) mosi (fromslave) ss (to slave) capture strobe cpha =1 msbit bi t 6 bit 5 bi t 4 bi t3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit4 bit3 bit2 bit1 lsbit mi so (frommaster) mosi ss (to slave) capture strobe cpha =0 note: this fi gure shoul d not be used as a repl acement for parametric i nformation. refer to the el ectri cal characteristics chapter. (fromslave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0) 1 st7flite0 57/111 serial peripheral interface (cont'd) 11.3.5 error flags 11.3.5.1 master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: the modf bit is set and an spi interrupt re- quest is generated if the spie bit is set. the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the spicsr register while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their orig- inal state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multi master configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application de- fault state. 11.3.5.2 overrun condition (ovr) an overrun condition occurs, when the master de- vice has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 11.3.5.3 write collision error (wcol) a write collision occurs when the software tries to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. see also section 11.3.3.2 slave select management. note: a oread collisiono will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 40). figure 40. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr write spidr 2nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 before the 2nd step read spicsr read spidr note: writing to the spidr regis- ter instead of reading it does not reset the wcol bit read spicsr or result result result 1 st7flite0 58/111 serial peripheral interface (cont'd) 11.3.5.4 single master and multimaster configurations there are two types of spi systems: single master system multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 41). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. figure 41. single master / multiple slave configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu 1 st7flite0 59/111 serial peripheral interface (cont'd) 11.3.6 low power modes 11.3.6.1 using the spi to wakeup the mcu from halt mode in slave configuration, the spi is able to wakeup the st7 device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is run- ning (interrupt vector fetch). if multiple data trans- fers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to per- form an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the st7 from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the st7 enters halt mode. so if slave selec- tion is configured as external (see section 11.3.3.2), make sure the master drives a low level on the ss pin when the slave enters halt mode. 11.3.7 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi oper- ation resumes when the mcu is woken up by an interrupt with aexit from halt modeo ca- pability. the data received is subsequently read from the spidr register when the soft- ware is running (interrupt vector fetching). if several data are received before the wake- up event, then an overrun error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes yes master mode fault event modf yes no overrun error ovr yes no 1 st7flite0 60/111 serial peripheral interface (cont'd) 11.3.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1, modf=1 or ovr=1 in the spicsr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss=0 (see section 11.3.5.1 master mode fault (modf)). the spe bit is cleared by reset, so the spi peripheral is not initially connected to the ex- ternal pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 10 spi master mode sck frequency. 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss=0 (see section 11.3.5.1 master mode fault (modf)). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the func- tions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 10. spi master mode sck frequency 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 1 st7flite0 61/111 serial peripheral interface (cont'd) control/status register (spicsr) read/write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only). this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. bit 6 = wcol write collision status (read only). this bit is set by hardware when a write to the spidr register is done during a transmit se- quence. it is cleared by a software sequence (see figure 40). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section 11.3.5.2). an interrupt is generated if spie = 1 in spicsr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 11.3.5.1 master mode fault (modf)). an spi interrupt can be generated if spie=1 in the spicsr register. this bit is cleared by a software sequence (an ac- cess to the spicsr register while modf=1 fol- lowed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable. this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe=1) 1: spi output disabled bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section 11.3.3.2 slave select management. 0: hardware management (ss managed by exter- nal pin) 1: software management (internal ss signal con- trolled by ssi bit. external ss pin free for gener- al-purpose i/o) bit 0 = ssi ss internal mode. this bit is set and cleared by software. it acts as a `chip select' by controlling the level of the ss slave select signal when the ssm bit is set. 0 : slave selected 1 : slave deselected data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will initiate transmission/reception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value lo- cated in the buffer and not the content of the shift register (see figure 35). 70 spif wcol ovr modf - sod ssm ssi 70 d7 d6 d5 d4 d3 d2 d1 d0 1 st7flite0 62/111 1 st7flite0 63/111 serial peripheral interface (cont'd) table 11. spi register map and reset values address (hex.) register label 76543210 31 spidr reset value msb xxxxxxx lsb x 32 spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 33 spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0 1 st7flite0 64/111 11.4 8-bit a/d converter (adc) 11.4.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 5 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 5 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 11.4.2 main features n 8-bit conversion n up to 5 channels with multiplexed input n linear successive approximation n dual input range 0 to v dd or 0v to 250mv n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) n fixed gain operational amplifier (x8) 11.4.3 functional description 11.4.3.1 analog power supply the block diagram is shown in figure 42. v dd and v ss are the high and low level reference voltage pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. for more details, refer to the electrical character- istics section. 11.4.3.2 input voltage amplifier the input voltage can be amplified by a factor of 8 by enabling the ampon bit in the adamp register. when the amplifier is enabled, the input range is 0v to 250 mv. for example, if v dd = 5v, then the adc can con- vert voltages in the range 0v to 250mv with an ideal resolution of 2.4mv (equivalent to 11-bit res- olution with reference to a v ss to v dd range). for more details, refer to the electrical character- istics section. note: the amplifier is switched on by the adon bit in the adccsr register, so no additional start- up time is required when the amplifier is selected by the ampon bit. figure 42. adc block diagram ch2 ch1 0 eoc speedadon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux r adc c adc d2 d1 d3 d7 d6 d5 d4 d0 adcdr 3 f adc hold control x1or x8 ampon bit (adcamp register) f cpu 0 1 1 0 div 2 div 4 slow bit (adcamp register) 7 0 1 st7flite0 65/111 8-bit a/d converter (adc) (cont'd) 11.4.3.3 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than or equal to v dda (high-level voltage reference) then the conversion result in the dr register is ffh (full scale) without overflow indication. if input voltage (v ain ) is lower than or equal to v ssa (low-level voltage reference) then the con- version result in the dr register is 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdr register. the accuracy of the conversion is described in the parametric section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 11.4.3.4 a/d conversion phases the a/d conversion is based on two conversion phases as shown in figure 43: n sample capacitor loading [duration: t sample ] during this phase, the v ain input voltage to be measured is loaded into the c adc sample capacitor. n a/d conversion [duration: t hold ] during this phase, the a/d conversion is computed (8 successive approximations cycles) and the c adc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. n the total conversion time: t conv = t sample +t hold while the adc is on, these two phases are contin- uously repeated. at the end of each conversion, the sample capaci- tor is kept loaded with the previous measurement load. the advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 11.4.3.5 software procedure refer to the control/status register (csr) and data register (dr) in section 11.4.6 for the bit defini- tions and to figure 43 for the timings. adc configuration the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: select the ch[2:0] bits to assign the analog channel to be converted. adc conversion in the csr register: set the adon bit to enable the a/d converter and to start the first conversion. from this time on, the adc performs a continuous conver- sion of the selected channel. when a conversion is complete the eoc bit is set by hardware. no interrupt is generated. the result is in the dr register and remains valid until the next conversion has ended. a write to the csr register (with adon set) aborts the current conversion, resets the eoc bit and starts a new conversion. figure 43. adc conversion timings 11.4.4 low power modes note : the a/d converter may be disabled by reset- ting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 11.4.5 interrupts none mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d con- verter requires a stabilization time before ac- curate conversions can be performed. adccsr write adon eoc bit set t sample t hold operation hold control t conv 1 st7flite0 66/111 8-bit a/d converter (adc) (cont'd) 11.4.6 register description control/status register (adccsr) read/write reset value: 0000 0000 (00h) bit 7 = eoc conversion complete this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete 1: conversion can be read from the dr register bit 6 = speed adc clock selection this bit is set and cleared by software. it is used together with the slow bit to configure the adc clock speed. refer to the table in the slow bit de- scription. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bit 4:3 = reserved. must always be cleared. bits 2:0 = ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *note : the number of pins and the channel selec- tion varies according to the device. refer to the de- vice pinout. data register (adcdr) read only reset value: 0000 0000 (00h) bits 7:0 = d[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. note : reading this register reset the eoc flag. amplifier control register (adcamp) read/write reset value: 0000 0000 (00h) bit 7:4 = reserved. forced by hardware to 0. bit 3 = slow slow mode this bit is set and cleared by software. it is used together with the speed bit to configure the adc clock speed as shown on the table below. bit 2 = ampon amplifier control bit this bit is set and cleared by software. 0: amplifier off 1: amplifier on note: when ampon=1 it is mandatory that f adc be less than or equal to 2 mhz. bit 1:0 = reserved. forced by hardware to 0. 70 eoc speed adon 0 0 ch2 ch1 ch0 channel pin* ch2 ch1 ch0 ain0 0 0 0 ain1 0 0 1 ain2 0 1 0 ain3 0 1 1 ain4 1 0 0 70 d7 d6 d5 d4 d3 d2 d1 d0 70 0 0 0 0 slow ampon 0 0 f adc slow speed f cpu /2 00 f cpu 01 f cpu /4 1x 1 st7flite0 67/111 table 12. adc register map and reset values address (hex.) register label 76543210 34h adcdr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 35h adccsr reset value eoc 0 speed 0 adon 000 ch2 0 ch1 0 ch0 0 36h adcamp reset value 0000 slow 0 ampon 0 00 1 st7flite0 68/111 12 instruction set 12.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 13. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow- ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) +1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 1 st7flite0 69/111 st7 addressing modes (cont'd) 12.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 12.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 12.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations 1 st7flite0 70/111 st7 addressing modes (cont'd) 12.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 14. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad- dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only functio n clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative 1 st7flite0 71/111 12.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc- tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf 1 st7flite0 72/111 instruction groups (cont'd) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > 1 st7flite0 73/111 instruction groups (cont'd) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z 1 st7flite0 74/111 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25 c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 s ). 13.1.2 typical values unless otherwise specified, typical data are based on t a =25 c, v dd =5v (for the 4.5v v dd 5.5v voltage range), v dd =3.75v (for the 3v v dd 4.5v voltage range) and v dd =2.7v (for the 2.4v v dd 3v voltage range). they are given only as design guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 44. figure 44. pin loading conditions 13.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 45. figure 45. pin input voltage c l st7 pin v in st7 pin 1 st7flite0 75/111 13.2 absolute maximum ratings stresses above those listed as aabsolute maxi- mum ratingso may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 13.2.1 voltage characteristics 13.2.2 current characteristics 13.2.3 thermal characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k w for reset, 10k w for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in st7flite0 77/111 operating conditions (cont'd) 13.3.2 operating conditions with low voltage detector (lvd) subject to general operating conditions for v dd ,f osc , and t a notes: 1. lvd typical data are based on t a =25 c. 2. the v dd rise time rate condition is needed to insure a correct device power-on and lvd reset. not tested in production. 13.3.3 auxiliary voltage detector (avd) thresholds subject to general operating conditions for v dd ,f osc , and t a notes: 1. avd typical data are based on t a =25 c. 13.3.4 internal rc oscillator and pll the st7 internal clock can be supplied by an internal rc oscillator and pll (selectable by option byte). symbol parameter condition s min typ 1) max unit v it+ (lvd) reset release threshold (v dd rise) high threshold med. threshold low threshold 4.00 3.40 2.65 4.25 3.60 2.90 4.50 3.80 3.15 v v it- (lvd) reset generation threshold (v dd fall) high threshold med. threshold low threshold 3.80 3.20 2.40 4.05 3.40 2.70 4.30 3.65 2.90 v hys lvd voltage threshold hysteresis v it+ (lvd) -v it- (lvd) 200 mv vt por v dd rise time rate 2) 20 m s/v t g(vdd) filtered glitch delay on v dd 2) not detected by the lvd 150 ns i dd(lvd ) lvd/avd current consumption 200 m a symbol parameter condition s min typ 1) max unit v it+ (avd) 1=>0 avdf flag toggle threshold (v dd rise) high threshold med. threshold low threshold 4.40 3.90 3.20 4.70 4.10 3.40 5.00 4.30 3.60 v v it- (avd) 0=>1 avdf flag toggle threshold (v dd fall) high threshold med. threshold low threshold 4.30 3.70 2.90 4.60 3.90 3.20 4.90 4.10 3.40 v hys avd voltage threshold hysteresis v it+ (avd) -v it- (avd) 150 mv symbol parameter conditions min typ max unit v dd(rc) internal rc oscillator operating voltage 2.4 5.5 v v dd(x4pll) x4 pll operating voltage 2.4 3.3 v dd(x8pll) x8 pll operating voltage 3.3 5.5 1 st7flite0 78/111 operating conditions (cont'd) the rc oscillator and pll characteristics are temperature-dependent and are grouped in four tables. 13.3.4.1 devices with `o6o order code suffix (tested for t a = -40 to +85 c) @ v dd = 4.5 to 5.5v 13.3.4.2 devices with `o3o order code suffix (tested for t a = -40 to +125 c) @ v dd = 4.5 to 5.5v notes: 1. data based on characterization results, not tested in production 2. rccr0 is a factory-calibrated setting for 1000khz with 0.2 accuracy @ t a =25 c, v dd =5v. see ainternal rc os- cillator adjustmento on page 20 3. guaranteed by design. 4. averaged over a 4ms period. after the locked bit is set, a period of t stab is required to reach acc pll accuracy. 5. after the locked bit is set acc pll is max. 10% until t stab has elapsed. see figure 11. symbol parameter conditi ons min typ max unit f rc internal rc oscillator fre- quency rccr = ff (reset value), t a =25 c,v dd =5v 760 khz rccr = rccr0 2) ,t a =25 c,v dd =5v 1000 acc rc accuracy of internal rc oscillator with rccr=rccr0 2) t a =25 c,v dd =5v -0.5 +0.5 % t a =25 c,v dd =4.5 to 5.5v -1 +1 % t a =-40 to +85 c,v dd =5v -2 +1 % t a =0 to +85 c,v dd =5v tbd tbd % i dd(rc) rc oscillator current con- sumption t a =25 c,v dd =5v 970 1) m a t su(rc) rc oscillator setup time t a =25 c,v dd =5v 10 2) m s f pll x8 pll input clock 1 1) mhz t lock pll lock time 5) 2ms t stab pll stabilization time 5) 4ms acc pll x8 pll accuracy f rc = 1mhz@t a =25 c,v dd =4.5 to 5.5v 0.1 4) % f rc = 1mhz@t a =-40 to +85 c,v dd =5v 0.1 4) % t w(jit) pll jitter period f rc = 1mhz 8 3) khz jit pll pll jitter ( d f cpu /f cpu )1 3) % i dd(pll) pll current consumption t a =25 c 600 1) m a symbol parameter conditi ons min typ max unit f rc internal rc oscillator fre- quency rccr = ff (reset value), t a =25 c,v dd =5v 760 khz rccr = rccr0 2) ,t a =25 c,v dd =5v 1000 acc rc accuracy of internal rc oscillator with rccr=rccr0 2) t a =25 c,v dd =5v -0.5 +0.5 % t a =25 c,v dd =4.5 to 5.5v -1 +1 % t a =-40 to +125 c,v dd =5v -2 +2 % i dd(rc) rc oscillator current con- sumption t a =25 c,v dd =5v 970 1) m a t su(rc) rc oscillator setup time t a =25 c,v dd =5v 10 2) m s f pll x8 pll input clock 1 1) mhz t lock pll lock time 5) 2ms t stab pll stabilization time 5) 4ms acc pll x8 pll accuracy f rc = 1mhz@t a =25 c,v dd =4.5 to 5.5v 0.1 4) % f rc = 1mhz@t a =-40 to 125 c,v dd =5v 0.1 4) % t w(jit) pll jitter period f rc = 1mhz 8 3) khz jit pll pll jitter ( d f cpu /f cpu )1 3) % i dd(pll) pll current consumption t a =25 c 600 1) m a 1 st7flite0 79/111 operating conditions (cont'd) 13.3.4.3 devices with `o6o order code suffix (tested for t a = -40 to +85 c) @ v dd = 2.7 to 3.3v 13.3.4.4 devices with `o3o order code suffix (tested for t a = -40 to +125 c) @ v dd = 2.7 to 3.3v notes: 1. data based on characterization results, not tested in production 2. rccr1 is a factory-calibrated setting for 700mhz with 0.2 accuracy @ t a =25 c, v dd =3v. see ainternal rc os- cillator adjustmento on page 20. 3. guaranteed by design. 4. averaged over a 4ms period. after the locked bit is set, a period of t stab is required to reach acc pll accuracy 5. after the locked bit is set acc pll is max. 10% until t stab has elapsed. see figure 11. symbol parameter condit ions min typ max unit f rc internal rc oscillator fre- quency rccr = ff (reset value), t a =25 c, v dd = 3.0v 560 khz rccr=rccr1 2) ,t a =25 c,v dd = 3v 700 acc rc accuracy of internal rc oscillator when calibrated with rccr=rccr1 1)2) t a =25 c,v dd =3v -2 +2 % t a =25 c,v dd =2.7 to 3.3v -20 +20 % t a =-40 to +85 c,v dd =3v -5 10 % i dd(rc) rc oscillator current con- sumption t a =25 c,v dd =3v 700 1) m a t su(rc) rc oscillator setup time t a =25 c,v dd =3v 10 2) m s f pll x4 pll input clock 1 1) mhz t lock pll lock time 5) 2ms t stab pll stabilization time 5) 4ms acc pll x4 pll accuracy f rc = 1mhz@t a =25 c,v dd =2.7 to 3.3v 0.1 4) % f rc = 1mhz@t a =40 to +85 c,v dd = 3v 0.1 4) % t w(jit) pll jitter period f rc = 1mhz 8 3) khz jit pll pll jitter ( d f cpu /f cpu )1 3) % i dd(pll) pll current consumption t a =25 c190 1) m a symbol parameter condit ions min typ max unit f rc internal rc oscillator fre- quency rccr = ff (reset value), t a =25 c, v dd = 3v 560 khz rccr=rccr1 2) ,t a =25 c,v dd = 3v 700 acc rc accuracy of internal rc oscillator when calibrated with rccr=rccr1 1)2) f rc =1mhz@t a =25 c,v dd =3v -2 +2 % f rc =1mhz@t a =25 c,v dd =2.7 to 3.3v -20 +20 % f rc =1mhz@t a =-40 to +125 c,v dd =3v tbd tbd % i dd(rc) rc oscillator current con- sumption t a =25 c,v dd =3v 700 1) m a t su(rc) rc oscillator setup time t a =25 c,v dd =3v 10 2) m s f pll x4 pll input clock 1 1) mhz t lock pll lock time 5) 2ms t stab pll stabilization time 5) 4ms acc pll x4 pll accuracy f rc = 1mhz@t a =25 c,v dd =2.7 to 3.3v 0.1 4) % f rc = 1mhz@t a =-40 to +85 c,v dd = 3v 0.1 4) % t w(jit) pll jitter period f rc = 1mhz 8 3) khz jit pll pll jitter ( d f cpu /f cpu )1 3) % i dd(pll) pll current consumption t a =25 c190 1) m a 1 st7flite0 80/111 operating conditions (cont'd) figure 47. pll d f cpu /f cpu versus time figure 48. rc osc freq vs v dd (calibrated with rcc1: 3v @ 25 c) figure 49. pllx4 output vs clkin frequency note: f osc =f clkin /2*pll4 figure 50. pllx8 output vs clkin frequency note: f osc =f clkin /2*pll8 t w(jit) d f cpu /f cpu t min max 0 400000 450000 500000 550000 600000 650000 700000 750000 800000 850000 900000 950000 1000000 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 vdd (v) output freq (hz) 0 1 2 3 4 5 6 7 1 1.5 2 2.5 3 external input clock frequency (mhz) output frequency (mhz) 3.3 3 2.7 0 2 4 6 8 10 12 0.85 0.9 1 1.5 2 2.5 external input clock frequency (mhz) output frequency (mhz) 5.5 5 4.5 4 1 st7flite0 81/111 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). 13.4.1 run and slow modes figure 51. typical i dd in run vs. f cpu figure 52. typical i dd in slow vs. f cpu notes: 1. typical data are based on t a =25 c, v dd =5v, v dd =3.3v and v dd =2.7v. 2. data based on characterization results, tested in production at v dd max. and f cpu max @ t a =-40 to +85 c. 3. cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 4. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. note 1: data based on product characterization, not tested in production. symbol parameter conditions typ 1) max unit i dd supply current in run mode 3) 5v f clkin =2mhz, f cpu =1mhz f clkin =8mhz, f cpu =4mhz f clkin =16mhz, f cpu =8mhz 0.66 2.30 4.50 9.0 2) ma supply current in slow mode 4) f clkin =2mhz, f cpu =62.5khz f clkin =8mhz, f cpu =250khz f clkin =16mhz, f cpu =500khz 0.17 0.33 0.55 1.1 2) supply current in run mode 3) 3.3v f clkin =2mhz, f cpu =1mhz f clkin =8mhz, f cpu =4mhz f clkin =16mhz, f cpu =8mhz 0.40 1.40 2.80 supply current in slow mode 4) f clkin =2mhz, f cpu =62.5khz f clkin =8mhz, f cpu =250khz f clkin =16mhz, f cpu =500khz 0.11 0.16 0.32 supply current in run mode 3) 2.7v f clkin =2mhz, f cpu =1mhz f clkin =8mhz, f cpu =4mhz 0.34 1.10 supply current in slow mode 4) f clkin =2mhz, f cpu =62.5khz f clkin =8mhz, f cpu =250khz 0.01 0.16 0.000 0.001 0.002 0.003 0.004 0.005 2.4 2.7 3.7 4.5 5 5.5 vdd (v) idd (a) 8mhz 4mhz 1mhz 0.0000 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 2.4 2.7 3.7 4.5 5 5.5 vdd (v) idd (a) 500khz 250khz 125khz symbol parameter conditions max unit d i dd( d ta) supply current variation vs. temperature 1) run mode with constant v dd and f cpu 10 % 1 st7flite0 82/111 wait and slow wait modes figure 53. typical i dd in wait vs. f cpu figure 54. typical i dd in slow-wait vs. f cpu notes: 1. typical data are based on t a =25 c, v dd =5v and v dd =3.3v. 2. data based on characterization results, tested in production at v dd max. and f cpu max.@ t a =-40 to +85 c. 3. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 4. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. symbol parameter conditions typ 1) max 2) unit i dd supply current in wait mode 3) 5v f clkin =2mhz, f cpu =1mhz f clkin =8mhz, f cpu =4mhz f clkin =16mhz, f cpu =8mhz 0.8 1.3 2.5 5 2) ma supply current in slow wait mode 4) f clkin =2mhz, f cpu =62.5khz f clkin =8mhz, f cpu =250khz f clkin =16mhz, f cpu =500khz 0.35 0.75 0.8 1.6 2) supply current in wait mode 3) 3.3v f clkin =2mhz, f cpu =1mhz f clkin =8mhz, f cpu =4mhz f clkin =16mhz, f cpu =8mhz 0.3 0.5 1.0 supply current in slow wait mode 4) f clkin =2mhz, f cpu =62.5khz f clkin =8mhz, f cpu =250khz f clkin =16mhz, f cpu =500khz 0.09 0.13 0.25 supply current in wait mode 3) 2.7v f clkin =2mhz, f cpu =1mhz f clkin =8mhz, f cpu =4mhz 0.22 0.45 supply current in slow wait mode 4) f clkin =2mhz, f cpu =62.5khz f clkin =8mhz, f cpu =250khz 0.15 0.20 0.000 0.001 0.001 0.002 0.002 2.4 2.7 3.7 4.5 5 5.5 vdd (v) idd (a) 8mhz 4mhz 1mhz 0.0000 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 2.4 2.7 3.7 4.5 5 5.5 vdd (v) idd (a) 500khz 250khz 125khz 1 st7flite0 83/111 13.4.2 halt mode 13.4.3 on-chip peripherals 13.5 clock and timing characteristics subject to general operating conditions for v dd ,f osc , and t a . 13.5.1 general timings notes: 1. data based on a differential i dd measurement between reset configuration (timer stopped) and a timer running in pwm mode at f cpu =8mhz. 2. data based on a differential i dd measurement between reset configuration and a permanent spi master communica- tion (data sent equal to 55h). 3. data based on a differential i dd measurement between reset configuration and continuous a/d conversions with am- plifier off. 4. guaranteed by design. not tested in production. 5. data based on typical application software. 6. time measured between interrupt event and interrupt vector fetch. dt c(inst) is the number of t cpu cycles needed to fin- ish the current instruction execution. symbol parameter condition s typ max unit i dd supply current in halt mode v dd =5.5v -40 c t a +85 c <1 10 m a -40 c t a +125 c 100 symbol parameter conditions typ unit i dd(at) 12-bit auto-reload timer supply current 1) f cpu =4mhz v dd = 3.0v 50 m a f cpu =8mhz v dd = 5.0v 150 i dd(spi) spi supply current 2) f cpu =4mhz v dd = 3.0v 50 f cpu =8mhz v dd = 5.0v 300 i dd(adc) adc supply current when converting 3) f adc =4mhz v dd = 3.0v 780 v dd = 5.0v 1100 symbol parameter 4) conditi ons min typ 5) max unit t c(inst) instruction cycle time 2 3 12 t cpu f cpu =8mhz 250 375 1500 ns t v(it) interrupt reaction time 6) t v(it) = d t c(inst) +10 10 22 t cpu f cpu =8mhz 1.25 2.75 m s 1 st7flite0 84/111 13.6 memory characteristics subject to general operating conditions for v dd ,f osc , and t a unless otherwise specified. 13.6.1 ram and hardware registers 13.6.2 flash program memory 13.6.3 eeprom data memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg- isters (only in halt mode). guaranteed by construction, not tested in production. 2. up to 32 bytes can be programmed at a time. 3. the data retention time increases when the t a decreases. 4. data based on reliability test results and monitored in production. 5. data based on characterization results, not tested in production. 6. guaranteed by design. not tested in production. 7. design target value pending full product characterization. symbol parameter conditi ons min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v symbol parameter conditions min typ max unit t prog programming time for 1~32 bytes 2) t a =- 40 to +85 c515ms programming time for 1.5kbytes t a = +25 c 0.24 0.72 t ret data retention 4) t a = +55 c 3) 20 years n rw write erase cycles t a = +25 c 10000 7) cycles i dd supply current read / write / erase modes f cpu = 8mhz, v dd = 5.5v 2.6 6) ma no read/no write mode 100 m a power down mode / halt 0 0.1 m a symbol parameter conditions min typ max unit t prog programming time for 1~32 bytes t a =- 40 to +85 c515ms t ret data retention 4) t a =+55 c 3) 20 years n rw write erase cycles t a = +25 c 300000 7) cycles 1 st7flite0 85/111 13.7 emc characteristics susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). n esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. n ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. figure 55. emc recommended star network power supply connection 2) notes: 1. data based on characterization results, not tested in production. 2. the suggested 10 m f and 0.1 m f decoupling capacitors on the power supply lines are proposed as a good price vs. emc performance tradeoff. they have to be put as close as possible to the device power supply pins. other emc recommen- dations are given in other sections (i/os, reset, oscx pin characteristics). symbol parameter condition s neg 1) pos 1) unit v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-2 -1 1 kv v fftb fast transient voltage burst limits to be ap- plied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-4 -4 4 v dd v ss 0.1 m f 10 m f v dd st72xxx v ssa v aref 0.1 m f power supply source st7 digital noise filtering external noise filtering 1 st7flite0 86/111 emc characteristics (cont'd) 13.7.2 absolute electrical sensitivity based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, re- fer to the an1181 st7 application note. 13.7.2.1 electro-static discharge (esd) electro-static discharges (3 positive then 3 nega- tive pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). two models are usually simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. see figure 56 and the following test sequences. human body model test sequence c l is loaded through s1 by the hv pulse gener- ator. s1 switches position from generator to r. a discharge from c l through r (body resistance) to the st7 occurs. s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. machine model test sequence c l is loaded through s1 by the hv pulse gener- ator. s1 switches position from generator to st7. a discharge from c l to the st7 occurs. s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. r (machine resistance), in series with s2, en- sures a slow discharge of the st7. absolute maximum ratings figure 56. typical equivalent esd circuits notes: 1. data based on characterization results, not tested in production. symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25 c 4000 v v esd(mm) electro-static discharge voltage (machine model) t a = +25 c tbd st7 s2 r=1500 w s1 high voltage c l = 100pf pulse generator st7 s2 high voltage c l = 200pf pulse generat or r=10k~10m w s1 human body model machine model 1 st7flite0 87/111 emc characteristics (cont'd) 13.7.2.2 static and dynamic latch-up n lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable i/o pin) and a power supply switch sequence are performed on each sample. this test conforms to the eia/ jesd 78 ic latch-up standard. for more details, refer to the an1181 st7 application note. n dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 57. for more details, refer to the an1181 st7 application note. electrical sensitivities figure 57. simplified diagram of the esd generator for dlu notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2. schaffner nsg435 with a pointed test finger. symbol parameter conditions class 1) lu static latch-up class t a = +25 c t a = +85 c a tbd dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25 c a r ch =50m w r d =330 w c s = 150pf esd hv relay dischar ge tip discharge return connection generator 2) st7 v dd v ss 1 st7flite0 88/111 emc characteristics (cont'd) 13.7.3 esd pin protection strategy to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. the stress generally affects the circuit el- ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements to be pro- tected must not receive excessive current, voltage or heating within their structure. an esd network combines the different input and output esd protections. this network works, by al- lowing safe discharge paths for the pins subjected to esd stress. two critical esd stress cases are presented in figure 58 and figure 59 for standard pins and in figure 60 and figure 61 for true open drain pins. standard pin protection to protect the output structure the following ele- ments are added: a diode to v dd (3a) and a diode from v ss (3b) a protection device between v dd and v ss (4) to protect the input structure the following ele- ments are added: a resistor in series with the pad (1) a diode to v dd (2a) and a diode from v ss (2b) a protection device between v dd and v ss (4) figure 58. positive stress on a standard pad vs. v ss figure 59. negative stress on a standard pad vs. v dd in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path path to avoid in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path 1 st7flite0 89/111 emc characteristics (cont'd) true open drain pin protection the centralized protection (4) is not involved in the discharge of the esd stresses applied to true open drain pads due to the fact that a p-buffer and diode to v dd are not implemented. an additional local protection between the pad and v ss (5a & 5b) is implemented to completely absorb the posi- tive esd discharge. multisupply configuration when several types of ground (v ss ,v ssa , ...) and power supply (v dd ,v aref , ...) are available for any reason (better noise immunity...), the structure shown in figure 62 is implemented to protect the device against esd. figure 60. positive stress on a true open drain pad vs. v ss figure 61. negative stress on a true open drain pad vs. v dd figure 62. multisupply configuration in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path path to avoid (5a) (5b) in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path (3b) (3b) v aref v ssa v aref v dd v ss back to back diode between grounds v ssa 1 st7flite0 90/111 13.8 i/o port pin characteristics 13.8.1 general characteristics subject to general operating conditions for v dd ,f osc , and t a unless otherwise specified. figure 63. two typical applications with unused i/o pin figure 64. typical i pu vs. v dd with v in =v ss notes: 1. unless otherwise specified, typical data are based on t a =25 c and v dd =5.0v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure 63). data based on design simulation and/or technology characteristics, not tested in production. 5. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de- symbol parameter conditio ns min typ 1) max unit v il input low level voltage 2) (input under v ilmax is guaranteed to be read as logic low) 0.3xv dd v v ih input high level voltage 2) (in- put over v ihmin is guaranteed to be read as logic high) 0.7xv dd v hys schmitt trigger voltage hyster- esis 3) 400 mv i l input leakage current v ss v in v dd 1 m a i s static current consumption 4) floating input mode 200 r pu weak pull-up equivalent resistor 5) v in = v s s v dd =5v t a 85 c v dd =5v t a 85 c 50 50 90 120 150 k w v dd =3.3v t a 85 c 80 2) 130 180 2) v dd =2.7v t a 85 c 140 2) 200 260 2) c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time 6) c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 6) 25 t w(it)in external interrupt pulse time 7) 1t cpu 10k w unused i/o port st7xxx 10k w unused i/o port st7xxx v dd to be characterized 1 st7flite0 91/111 scribed in figure 64). 6. data based on characterization results, not tested in production. 7. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. 1 st7flite0 92/111 i/o port pin characteristics (cont'd) 13.8.2 output driving current subject to general operating conditions for v dd ,f cpu , and t a unless otherwise specified. figure 65. typical v ol at v dd =5v (standard) figure 66. typical v ol at v dd =5v (high-sink) symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 65 and figure 68) v dd =5v i io =+5ma t a 85 c t a 85 c 1.0 1.2 v i io =+2ma t a 85 c t a 85 c 0.4 0.5 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 66 and figure 69) i io =+20ma,t a 85 c t a 85 c 1.3 1.5 i io =+8ma t a 85 c t a 85 c 0.75 0.85 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 67 and figure 70) i io =-5ma, t a 85 c t a 85 c v dd -1.4 v dd -1.6 i io =-2ma t a 85 c t a 85 c v dd -0.7 v dd -1.0 v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 65 and figure 68) v dd =3.3v i io =+2ma t a 85 c t a 85 c 0.5 0.6 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 66 and figure 69) i io =+8ma t a 85 c t a 85 c 0.5 0.6 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 67 and figure 70) i io =-2ma t a 85 c t a 85 c v dd -0.6 v dd -1.0 v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 65 and figure 68) v dd =2.7v i io =+2ma t a 85 c t a 85 c 0.6 0.7 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 66 and figure 69) i io =+8ma t a 85 c t a 85 c 0.6 0.7 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 67 and figure 70) i io =-2ma t a 85 c t a 85 c v dd -0.8 v dd -1.0 to be characterized to be characterized 1 st7flite0 93/111 i/o port pin characteristics (cont'd) figure 67. typical v dd -v oh at v dd =5v notes: 1. the i io current sunk must always respect the absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . to be characterized 1 st7flite0 94/111 i/o port pin characteristics (cont'd) figure 68. typical v ol vs. v dd (standard i/os) figure 69. typical v ol vs. v dd (high-sink i/os) figure 70. typical v dd -v oh vs. v dd to be characterized to be characterized to be characterized 1 st7flite0 95/111 13.9 control pin characteristics 13.9.1 asynchronous reset pin subject to general operating conditions for v dd ,f osc , and t a unless otherwise specified. figure 71. typical application with reset pin 8)9)10) notes: 1. unless otherwise specified, typical data are based on t a =25 c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. the i io current sunk must always respect the absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 5. the r on pull-up equivalent resistor is based on a resistive transistor. specfied for voltages on reset pin between v ilmax and v dd 6. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. 7. the reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy environments. 8. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). 9. whatever the reset source is (internal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 13.9.1 on page 95 . otherwise the reset will not be taken into account internally. 10. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-p for example) is less than the absolute maximum value spec- symbol parameter conditio ns min typ 1) max unit v il input low level voltage 2) (input under v il- max is guaranteed to be read as logic low) 0.3xv dd v v ih input high level voltage 2) (input over v ihmin is guaranteed to be read as logic high) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 2v v ol output low level voltage 4) v dd =5v i io =+5ma t a 85 c t a 85 c 0.5 1.0 1.2 v i io =+2ma t a 85 c t a 85 c 0.2 0.4 0.5 r on pull-up equivalent resistor 5) v dd =5v. 10 25 40 k w v dd =3v. tbd tbd tbd t w(rstl)out generated reset pulse duration external pin or internal reset sources 30 m s t h(rstl)in external reset pulse hold time 6) 20 m s t g(rstl)in filtered glitch duration 7) 100 ns reset v dd watch dog st72xxx lvd internal r on 0.1 m f v dd 0.1 m f v dd 4.7k w external reset circuit 8) reset control o ption al user illegal opcode 1 st7flite0 96/111 ified for i inj(reset) in section 13.2.2 on page 75. 1 st7flite0 97/111 13.10 communication interface characteristics 13.10.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss, sck, mosi, miso). figure 72. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or characterisation results, not tested in production. 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditio ns min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss) ss setup time slave 120 ns t h(ss) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out see note 2 cpol=0 cpol=1 t su(ss) t h(ss) t dis(so) t h(so) see note 2 bit1 in 1 st7flite0 98/111 communication interface characteristics (cont'd) figure 73. spi slave timing diagram with cpha=1 1) figure 74. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss) t h(ss) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 see note 2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) 1 st7flite0 99/111 13.11 8-bit adc characteristics subject to general operating condition for v dd ,f osc , and t a unless otherwise specified. figure 75. typical application with adc notes: 1. unless otherwise specified, typical data are based on t a =25 c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refers to v dd and v ss . 3. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k w ). data based on characterization results, not tested in production. 4. the stabilization time of the ad converter is masked by the first tload. the first conversion after the enable is then always valid. 5. guaranteed by design. not tested in production. 13.11.0.1 general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to shield the the noise-sensi- tive, analog physical interface from noise-generat- ing cmos logic signals. properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital out- puts on the same i/o port as the a/d input being converted. symbol parameter conditions min typ 1) max unit f adc adc clock frequency 4 mhz v ain conversion voltage range 2) v ssa v dda v r ain external input resistor 10 3) k w c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu =8mhz, f adc =4mhz 0 4) m s t conv conversion time (t sample +t hold )3 t sample sample capacitor loading time 4 1/f adc t hold hold conversion time 8 i adc analog part 1 5) ma digital part 0.2 5) ainx st72xxx v dd i l 1 m a v t 0.6v v t 0.6v c adc 6pf v ain r ain 8-bit a/d conversion 2k w( max ) 1 st7flite0 100/111 adc characteristics (cont'd) adc accuracy with v dd =5.0v figure 76. adc accuracy characteristics with amplifier disabled notes: 1) data based on characterization results over the whole temperature range, monitored in production. 2) adc accuracy vs. negative injection current: for i inj- =0.8ma, the typical leakage induced inside the die is 1.6 m a and the effect on the adc accuracy is a loss of 1 lsb for each 10k w increase of the external analog source impedance. this effect on the adc accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an input with analog capability, adjacent to the enabled analog input -at5vv dd supply, and worst case temperature. symbol parameter conditions typ max unit |e t | total unadjusted error 2) f cpu =8mhz, f adc =4mhz 2 lsb e o offset error 2) 1.5 1) e g gain error 2) 1.5 1) |e d | differential linearity error 2) 1 1) |e l | integral linearity error 2) 1 1) e o e g 1lsb ideal 1lsb ideal v dda v ssa 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =diff erential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 253 254 255 256 (1) (2) e t e d e l (3) v dda v ssa 1 st7flite0 101/111 adc characteristics (cont'd) figure 77. adc accuracy characteristics with amplifier enabled note: when the ampon bit in the adcdrl register is set, it is mandatory that f adc be less than or equal to 2 mhz. (if f cpu =8mhz. then speed=0, slow=1). notes: 1) data based on characterization results over the whole temperature range, not tested in production. 2) for precise conversion results it is recommended to calibrate the amplifier at the following two points: offset at v inmin =0v gain at full scale (for example v in =250mv) 3) monotonicity guaranteed if v in increases or decreases in steps of min. 5mv. e o e g 1lsb ideal v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =diff erential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 100 101 102 103 (1) (2) e t e d e l (3) 250 mv v ss 1lsb ideal v dda v ssa 103 8 -------------------------------------- = symbol parameter condit ions min typ max unit v dd(amp) amplifier operating voltage 4.5 5.5 v v in amplifier input voltage v dd =5v 0 250 mv v offset amplifier offset voltage 200 mv v step step size for monotonicity 3) 5mv linearity output voltage response linear gain factor amplified analog input gain 2) 7 1) 89 1) vmax output linearity max voltage v inmax = 250mv, v dd =5v 2.05 2.2 2.4 v vmin output linearity min voltage 0 1) 0.22 0.25 v 1 st7flite0 102/111 14 package characteristics 14.1 package mechanical data figure 78. 16-pin plastic dual in-line package, 300-mil width figure 79. 16-pin plastic small outline package, 150-mil width dim. mm inches min typ max min typ max a 5.33 0.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 b3 0.76 0.99 1.14 0.030 0.039 0.045 c 0.20 0.25 0.36 0.008 0.010 0.014 d 18.67 19.18 19.69 0.735 0.755 0.775 d1 0.13 0.005 e 2.54 0.100 e 7.62 7.87 8.26 0.300 0.310 0.325 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 eb 10.92 0.430 number of pins n 16 c e e1 eb l a a2 a1 e b b2 b3 d1 d dim. mm inches min typ max min typ max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 9.80 10.00 0.386 0.394 e 3.80 4.00 0.150 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 a 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 16 0016020 e h a1 c a 45 a1 a b d e 16 9 1 8 l st7flite0 103/111 14.2 thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation determined by the user. 2. the average chip-junction temperature can be obtained from the formula t j =t a +p d x rthja. symbol ratings value unit r thja package thermal resistance (junction to ambient) tbd c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c st7flite0 104/111 14.3 soldering and glueability information recommended soldering information given only as design guidelines. figure 80. recommended wave soldering profile (with 37% sn and 63% pb) figure 81. recommended reflow soldering oven profile (mid jedec) recommended glue for smd plastic packages: n heraeus: pd945, pd955 n loctite: 3615, 3298 250 200 150 100 50 0 40 80 120 160 time [sec] temp. [ c] 20 60 100 140 5 sec cooling phase (room temperature) preheating 80 c phase soldering phase 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [ c] ramp up 2 c/sec for 50sec 90 sec at 125 c 150 sec above 183 c ramp down natural 2 c/sec max tmax=220+/-5 c for 25 sec st7flite0 105/111 15 device configuration and ordering information each device is available for production in a user programmable version (flash). flash devices are shipped to customers with a default program memory content (ffh). the osc option bit is pro- grammed to 0 by default. 15.1 option bytes the two option bytes allow the hardware configu- ration of the microcontroller to be selected. the option bytes can be accessed only in pro- gramming mode (for example using a standard st7 programming tool). option byte 0 bit 7:4 = reserved, must always be 1. bit 3:2 = sec[1:0] sector 0 size definition these option bits indicate the size of sector 0 ac- cording to the following table. bit 1 = fmp_r read-out protection this option indicates if the flash program mem- ory and data eeprom is protected against pira- cy. the read-out protection blocks access to the program and data areas in any mode except user mode and iap mode. erasing the option bytes when the fmp_r option is selected will cause the whole memory to be erased first. 0: read-out protection off 1: read-out protection on bit 0 = fmp_w flash write protection this option indicates if the flash program mem- ory is write protected. warning: when this option is selected, the pro- gram memory (and the option bit itself) can never be erased or programmed again. 0: write protection off 1: write protection on option byte 1 bit 7 = pllx4x8 pll factor selection. 0: pllx4 1: pllx8 bit 6 = plloff pll disable. 0: pll enabled 1: pll disabled (by-passed) bit 5 = reserved, must always be 1. bit 4 = osc rc oscillator selection 0: rc oscillator on 1: rc oscillator off sector 0 size sec1 sec0 0.5k 00 1k 01 1.5k 1x f osc option bits osc plloff pllx4x8 0-8 mhz (with external clock 0-8 mhz) 11 x 4 mhz (with external clock 1 mhz) 10 0 8 mhz (with external clock 1 mhz) 10 1 1 mhz 0 1 x 4 mhz 0 0 0 8 mhz 0 0 1 option byte 1 15 8 option byte 0 70 pll x4x8 pll off osc lvd1 lvd0 wdg sw wdg halt reserved sec1 sec0 fmp r fmp w default value 1110111111111100 st7flite0 106/111 option bytes (cont'd) bit 3:2 = lvd[1:0] low voltage detection selection these option bits enable the lvd block with a se- lected threshold as shown in table 15. table 15. lvd threshold configuration bit 1 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) bit 0 = wdg halt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode 15.2 device ordering information figure 82. flash user programmable device types configuration lvd1 lvd0 lvd off 11 highest voltage threshold ( ~ 4.1v) 10 medium voltage threshold ( ~ 3.5v) 01 lowest voltage threshold ( ~ 2.8v) 00 device package temp. range 1= standard 0 to +70 c 6= industrial -40 to +85 c 3 = automotive -40 to +125 c b= plastic dual in line m= plastic small outline st7flite05y0 st7flite09y0 st7flite0 107/111 15.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: ? http//mcu.st.com. tools from these manufacturers include c compli- ers, emulators and gang programmers. stmicroelectronics tools three types of development tool are offered by st see table 16 and table 17 for more details. table 16. stmicroelectronics tools features table 17. dedicated stmicroelectronics development tools note : 1. in-circuit programming (icp) interface for flash devices. in-circuit emulation programming capabili ty 1) software included st7 in circuit debugging kit yes yes (all packages) st7 cd rom with: st7 assembly toolchain stvd7 powerful source level debugger for win 3.1, win 9x and nt c compiler demo versions st realizer for win 3.1 and win 95. windows programming tools for win 3.1, win 9x and nt st7 emulator yes, powerful emulation features including trace/ logic analyzer no st7 programming board no yes (all packages) suppor ted products st7 in circuit debugging kit st7 emulator st7 programming board st7flite05, st7flite09 st7flite0-indart st7mdt10-emu3 st7mdt10-epb st7flite0 108/111 15.4 st7 application notes identification descriptio n example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i c communicating between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso?d) an1042 st7 routine for i c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 descriptio n of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 permanent magnet dc motor drive. an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 using the st7 spi to emulate a 16-bit slave an1475 developing an st7265x mass storage application product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b product optimization an 982 using st7 with ceramic renator an1014 how to minimize the st7 power consumption st7flite0 109/111 15.5 to get more information to get the latest information on this product please use the st web server: http://mcu.st.com/ an1015 softw are techniques for improving microcontroller emc performance an1040 monito ring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1477 emulated data eeprom with xflash memory programming and tools an 978 key features of the stvd7 st7 visual debug package an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getti ng started with the st7 hiware c toolchain an1039 st7 math utility routines an1064 writing optimiz ed hiware c language for st7 an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug a st72324 target application an1478 porting an st7 panta project to codewarrior ide identification descriptio n st7flite0 110/111 16 summary of changes revision main changes date 2.0 modified ltcsr and sicsr reset values in table 2, ahardware register map,o on page 8 modified figure 4. typical icc interface added adata eeprom read-out protectiono on page 15 modified predefined calibration values in ainternal rc oscillator adjustmento on page 20 added figure 11. pll output frequency timing diagram modified figure 14. reset block diagram and added note and warning below figure modified figure 27 on page 38. modified table in section 9.4 on page 35. added section 10.4 on page 40 on unused i/o pins added caution on at timer ovf bit high level in section 11.2.6 on page 49 v dd min at 8mhz changed from 3.0 to 3.3 v in section 13.3.1 on page 76 updated asupply current characteristicso on page 81 updated section on aoperating conditions with low voltage detector (lvd)o on page 77 updated section on ainternal rc oscillator and pllo on page 77 default value of osc option bit changed to 0 in aoption byteso on page 105 dec-01 st7flite0 111/111 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a . http:// www.st.com |
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